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Design of High-performance Parallel BCH Decoder for Error Collection in MLC Flash Memory
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 Title & Authors
Design of High-performance Parallel BCH Decoder for Error Collection in MLC Flash Memory
Choi, Won-Jung; Lee, Je-Hoon; Sung, Won-Ki;
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 Abstract
This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.
 Keywords
Error Correction;BCH Code;Parallel Processing;Syndrome Generator;
 Language
Korean
 Cited by
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