JOURNAL BROWSE
Search
Advanced SearchSearch Tips
An Efficient Cache Management Scheme of Flash Translation Layer for Large Size Flash Memory Drives
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
An Efficient Cache Management Scheme of Flash Translation Layer for Large Size Flash Memory Drives
Choi, Hwan-Pil; Kim, Yong-Seok;
  PDF(new window)
 Abstract
Nowadays, large size flash memory drives with more than a couple of hundreds of gigabytes are common. This paper presents an efficient cache management scheme of flash translation layer, called TPC-FTL, for large size flash memory drives. Since flash drives of large size usually contain large size RAM, we can enhance the performance of page mapping cache by using more RAM for the cache. But if the size exceeds a threshold, the existing schemes are impractical for real devices, because the time for cache manipulation becomes too long. TPC-FTL manages the cache in translation page unit, not in logical page number unit used in existing schemes. Since a translation page covers a large number of logical page numbers (for example, 512 for 2KB size page), the number of cache elements can be reduced up to a practical level. A performance evaluation shows that average response time, an important performance measure, is better than existing schemes via the effect of utilizing spacial locality in addition to temporal locality.
 Keywords
SSD;Flash Memory;FTL;Page Mapping;Cache Management;
 Language
Korean
 Cited by
 References
1.
S. Lee, D. Park, T. Chung, D. Lee, S. Park, H. Song, "A log buffer based flash translation layer using fully associative sector translation," ACM Trans. Embedded Computing Sys. Vol. 6, No. 3, pp.1-27, 2007. crossref(new window)

2.
A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: a Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings," Proc. 14th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'09), New York, 2009.

3.
E. Goossaert, "Coding for SSDs - Part 2: Architecture of an SSD and Benchmarking," http://codecapsule.com/2014/02/12/coding-for-ssdspart-2-architecture-of-an-ssd-and-benchmarking/

4.
"Yet another flash file system," http://www.yaffs.net

5.
A. B. Bityutskiy, "JFFS3 design issues." http://www.linux-mtd.infradead.org

6.
C. Lee, D. Sim, J. Hwang, and S. Cho, "F2FS: A New File System for Flash Storage", Proc. 13th USENIX Conference on File and Storage Technologies (FAST '15), pp.273-286, Feb. 2015.

7.
D. Park, B. Debnath, and D. Du, "CFTL: An Adaptive Hybrid Flash Translation Layer with Efficient Caching Strategies," IEEE Trans. on Computers, pp. 1-15, Sep. 2011.

8.
C. Wang, W. Wong, "ADAPT: efficient workload-sensitive flash management based on adaptation, prediction and aggregation," Proc. IEEE 28th Symposium on Mass Storage Systems and Technologies (MSST), April 2012.

9.
J. Boukhobza, et al., "MaCACH: An Adaptive Cache-Aware Hybrid FTL Mapping Scheme Using Feedback Control for Effieient Page-Mapped Space Management," Journal of Systems Architecture, Elsevier, pp. 157-171, 2015.

10.
Samsung Electronics, "Samsung SSD 850 PRO Data Sheet, Rev.2.0," Jan. 2015. http://www.samsung.com/global/business/semiconduc tor/minisite/SSD/kr/html/ssd850pro/specifications.html

11.
"Storage Traces of UMass Trace Repository," http://traces.cs.umass.edu/index.php/Storage/Storage