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Design of High-Speed Parallel Multiplier on Finite Fields GF(3m)
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 Title & Authors
Design of High-Speed Parallel Multiplier on Finite Fields GF(3m)
Seong, Hyeon-Kyeong;
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In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields , and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.
Finite fields;Multiplier;Irreducible polynomial;Polynomial;GF;
 Cited by
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