Three Color Algorithm for Two-Layer Printed Circuit Boards Layout with Minimum Via

- Journal title : Journal of the Korea Society of Computer and Information
- Volume 21, Issue 3, 2016, pp.1-8
- Publisher : Korean Society of Computer Information
- DOI : 10.9708/jksci.2016.21.3.001

Title & Authors

Three Color Algorithm for Two-Layer Printed Circuit Boards Layout with Minimum Via

Lee, Sang-Un;

Lee, Sang-Un;

Abstract

The printed circuit board (PCB) can be used only 2 layers of front and back. Therefore, the wiring line segments are located in 2 layers without crossing each other. In this case, the line segment can be appear in both layers and this line segment is to resolve the crossing problem go through the via. The via minimization problem (VMP) has minimum number of via in layout design problem. The VMP is classified by NP-complete because of the polynomial time algorithm to solve the optimal solution has been unknown yet. This paper suggests polynomial time algorithm that can be solve the optimal solution of VMP. This algorithm transforms n-line segments into vertices, and p-crossing into edges of a graph. Then this graph is partitioned into 3-coloring sets of each vertex in each set independent each other. For 3-coloring sets , (i

Keywords

Via;Crossing;Coloring;Independent set;Two layer;

Language

Korean

References

1.

K. S. The, D. F. Wong, and J. Cong, "A Layout Modification Approach to Via Minimization," IEEE Transactions on Computer-Aided Design, Vol. 10, No. 4, pp. 536-541, Apr. 1991.

2.

L. Franuke, N. Tim, and P. Gregor, "Via Minimization in VLSI Chip Design - Application of a Planar Max-Cut Algorithm," Department of Computer Science, Faculty of Mathematics and Natural Sciences, Cologne University, Technical report, pp. 1-15, 2011.

3.

M. R. Garey and D. S. Johnson, "Crossing Number is NP-complete," SIAM Journal of Algorithmic Discrete Methods, Vol. 4, No. 3, pp. 312-316, 1983.

4.

N. I. Naclerio, S. MasudAa, and K. Nakajima, "The Via Minimization Problem is NP-complete," IEEE Transactions on Computers, Vol. 38, No. 2, pp. 1604-1608, Nov. 1989.

5.

R. Hojati, "Layout Optimization by Pattern Modification," Proceedings of the 27th ACM/IEEE Design Automation Conference, pp. 632-637, Jun. 1990.

6.

S. C. Fang, K. E. Chang, W. S. Feng, and S. J. Chen, "Constrained Via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems," Proceedings of the 28th ACM/IEEE Design Automation Conference, pp. 60-65, Jun. 1991.

7.

R. W. Chen, Y. Kajitani, and S. P. Chan, "A Graph -Theoretic Via Minimization Algorithm for Two-Layer Printed Circuit Boards," IEEE Transactions on Circuits and Systems, Vol. CAS-30, No. 5, pp. 284-299, May 1983.

8.

C. P. Hsu, "Minimum-Via Topological Routing," IEEE Transactions on Computer-Aided Design, Vol. CAD-2, No. 4, pp. 235-246, Oct. 1983.

9.

Y. S. Kuo, T. C. Chen, and W. K. Shih, "Fast Algorithm for Optimal Layer Assignment," Integration, the VLSI Journal, Vol. 7, No. 3, pp. 231-245, Sep. 1989.

10.

C. C. Chang and J. Cong, "An Efficient Approach to Multilayer Assignment with an Application to Via Minimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 5, pp. 608-620, May 1999.

11.

M. S. Malgorzata, "An Unconstrained Topological Via Minimization Problem for Two-Layer Routing," IEEE Transactions on Computer-Aided Design, Vol. CAD-3, No. 3, pp. 184-190, Jul. 1984.

12.

N. J. Naclerio, S. Masuda, and K. Nakajima, "Via Minimization for Gridless Layouts," Proceedings of the 24th ACM/IEEE Design Automation Conference, pp. 159-165, Jun. 1987.

13.

S. Thakur, K. Y. Chao, and D. F. Wong, "An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing," IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 207- 210, Apr. 1995.

14.

M. J. Chesielski, "Layer Assignment for VLSI Interconnect Delay Minimization," IEEE Transactions on Computer-Aided Design, Vol. 8, No. 6, pp. 702-707, Jun. 1989.

15.

K. Takahashi and T. Watanabe, "A Heuristic Algorithm to Solve Constrained Via Minimization for Three-Layer Routing Problems," Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Vol. 6, pp. 254-257, Jun. 1998.

16.

R. Noteboom and H. H. Ali, "A New Graph Coloring Algorithm for Constrained Via Minimization," Proceedings of the 37th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 363-366, Aug. 1994.

17.

M. Tang, K. Eshraghian, H. N. Cheung, "A Genetic Algorithm for Constrained Via Minimization," Proceedings of the 6th International Conference on Neural Information Processing, Vol. 2, pp. 435-440, Nov. 1999.

18.

P. Fouilhoux and A. R. Mahjoub, "An Exact Model for Multi-Layer Constrained Via Minimization," IEEE Transactions on CAD of ICS, Vol. xx , No. y, Jul. 2004.

19.

R. B. Lin and S. Y. Chen, "Conjugate Conflict Continuation Graphs for Multi-Layer Constrained Via Minimization," Information Sciences, Vol. 177, No. 12, pp. 2436-2447, Jun. 2007.

20.

P. Fouilhoux and A. R. Mahjoub, "Solving VLSI Design and DNA Sequencing Problems Using Bipartization of Graphs," Computational Optimization and Applications, Vol. 51, No. 2, pp. 749-781, Mar. 2012.

21.

N. A. Sherwani, "Algorithms for VLSI Physical Design Automation, chapter 8. Via Minimization and Over-the-Cell Routing, 3rd ed.," Kluwer Academic Publishers Norwell, 1999.

22.

X. Munoz, W. Unger, and I. Vrt'o, "One Sided Crossing Minimization is NP-hard for Sparse Graphs," In P. Mutzel and M. Junger, eds., Graph Drawing GD'01, LNCS 2265, pp. 115-123, Springer, 2001.

23.

M. Newton, O. Sykora, and I. Vrt'o, "Two New Heuristics for Two-Sides Bipartite Graph Drawing," Lecture Notes in Computer Science, Vol. 2528, pp. 465-485, Springer Berlin/Heidelberg, 2002.