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Design of the Multiplier in case of P
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 Title & Authors
Design of the Multiplier in case of P
Park, Chun-Myoung;
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 Abstract
This paper proposes the constructing method of effective multiplier based on the finite fields in case of P
 Keywords
Polynomial;primitive irreducible polynomial;arithmetic operation;module;transformation etc;
 Language
Korean
 Cited by
 References
1.
Jabir, A.M, Pradhan D.K. and Mathew J.,'GfXpress: A Technique for Synthesis and Optimization of Polynomials', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.698-711, Vol.27, Issue 4, 2008. crossref(new window)

2.
Tummeltshammer P., Hoe J.C. and Puschel M.,'Time-Multiplexed Multiple-Constant Multiplication', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1551-1563, vol.26, Issue 9, 2007. crossref(new window)

3.
Fenn S.T.J., Benaissa. M. and Taylor, D.,'Finite field inversion over the dual basis,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.134-137, Vol. 4, Issue 1, 1996. crossref(new window)

4.
Imana. J.L.,'Low Latency Polynomial Basis Multiplier,' IEEE Transactions on Circuits and Systems I, pp.935-946, Vol. 58, Issue 5, 2011.

5.
Psarakis, M., Gizopoulos, D. and Paschalis, A.'Built-in sequential fault self-testing of array multipliers,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.449-460, Vol. 24, Issue 3, 2005. crossref(new window)

6.
Paar C., Fleischmann P. and Soria-Rodriguez P.,'Fast arithmetic for public-key algorithms in Galois fields with composite exponents', IEEE Transactions on Computers, pp.1025-1034, Vol.48, Issue 10, 1999. crossref(new window)

7.
Poolakkaparambil M., Mathew J., Jabir. A.M. and Pradhan, D.K.,'A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1448-1458, Vol.23, Issue 8, 2015. crossref(new window)

8.
Dimitrakopoulos G. and Paliouras V.,'A novel architecture and a systematic graph-based optimization methodology for modulo multiplication,' IEEE Transactions on Circuits and Systems I, pp.354-370, Vol. 51, Issue 2, 2004.

9.
Jain S.K., Leilei Song and Parhi K.K.,'Efficient semisystolic architectures for finite-field arithmetic,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.101-113, Vol. 6, Issue 1, 1998. crossref(new window)

10.
Elleithy K.M. and Bayoumi M.A.,'A systolic architecture for modulo multiplication,' IEEE Transactions on Circuits and Systems II, pp.715-729, Vol. 42, Issue 11, 1995. crossref(new window)