Advanced SearchSearch Tips
FPGA Mapping Incorporated with Multiplexer Tree Synthesis
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
FPGA Mapping Incorporated with Multiplexer Tree Synthesis
Kim, Kyosun;
  PDF(new window)
The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.
Multiplexor tree synthesis;Field programmable gate array;Mapping;Functionally reduced and-inverter graph;
 Cited by
ABC: A System for Sequential Synthesis and Verification. Berkeley Logic Synthesis and Verification Group,, October, 2007.

V. Betz and J. Rose, "VPR: A New Packing, Placement And Routing Tool For FPGA Research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. pp.213-222, 1997.

L. Amaru, P-E Gaillardon, and G.D. Micheli, "Majority-Inverter Graph: A New Paradigm for Logic Optimization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2016.

N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, M. French, "Torc: Towards Open- Source Tool Flow," in Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.41-44, February, 2010.

C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings, "RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs" in Proceedings of the 21st International Workshop on Field-Programmable Logic and Applications, pp.349-355, September, 2011.

Xilinx Design Language Version 1.6, Xilinx, Inc., Xilinx ISE 6.1i Documentation in ise6.1i/help/data /xdl, July 2000.

K. Kim, "Evaluation Toolkit for K-FPGA Fabric Architectures," Journal of the IEEK, vol. 49-SD, no. 4, pp.157-167, April, 2012.

K. Kim, "Pre-Packing, Early Fixation, and Multi- Layer Density Analysis in Analytic Placement for FPGAs, Journal of the IEEK, vol. 51-SD, no. 10, pp.96-106, October, 2014.

Spartan-3 Generation FPGA User Guide, UG331, v1.6, Xilinx Inc., December 3, 2009.

A. Mishchenko, S. Chatterjee, R. Jiang, and R. K. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification". ERL Technical Report, EECS Dept., UC Berkeley, March 2005.

A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to Technology Mapping for LUT-Based FPGAs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, Issue 2, pp.240-253, February, 2007. crossref(new window)

A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and Sequential Mapping with Priority Cuts," Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp.354-361, November, 2007.

A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis," Proc. of Design Automation Conference, pp.532-535, July, 2006.

M. Guiney, E. Leavitt, "An Introduction to OpenAccess: an Open Source Data Model and API for IC Design," in Proceedings of Asia and South Pacific Conference on Design Automation, pp. 434-436, January, 2006.