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Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder
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 Title & Authors
Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder
Choi, Injun; Kim, Ji-Hoon;
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 Abstract
This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.
 Keywords
Non-binary LDPC code;Extended min-sum algorithm;Fully-parallel architecture;High-throughput;
 Language
Korean
 Cited by
 References
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