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Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design
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 Title & Authors
Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design
Lee, Kwang-Min; Park, Sungkyung;
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 Abstract
With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32
 Keywords
small area;low gate count;embedded processor;IoT (Internet of things);
 Language
Korean
 Cited by
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