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Separated Address/Data Network Design for Bus Protocol compatible Network-on-Chip
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 Title & Authors
Separated Address/Data Network Design for Bus Protocol compatible Network-on-Chip
Chung, Seungh Ah; Lee, Jae Hoon; Kim, Sang Heon; Lee, Jae Sung; Han, Tae Hee;
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As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.
NoC;Topology generation;Latency;Contention;Bus protocol;
 Cited by
P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures," IEEE Trans. Computers, Vol. 54, no. 8, pp. 1025-1040, Aug. 2005. crossref(new window)

B. A. A. Zitouni and R. Tourki, "Design and implementation of network interface compatible OCP for packet based NoC," in Proc. of Int. Conf. Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1-8, Mar. 2010.

C. Ababei, "Efficient Congestion-oriented Custom Network-on-Chip Topology Synthesis," in Proc. of Int. Conf. Reconfigurable Computing and FPGAs (ReConFig), pp. 352-357, Dec. 2010.

S. Deniziak and R. Tomaszewski, "Contentionavoiding custom topology generation for network-on-chip," in Proc. of Int. Symp. Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 234-237, April 2009.

A. Shacham, K. Bergman, and L. P. Carloni, "On the Design of a Photonic Network-on-Chip," in Proc. of Int. Symp. Networks-on-Chip (NOCS), pp. 53-64, May 2007.

J. Balfour and W. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Proc. of Int. Conf. Supercomputing (ICS), pp. 298-198, June 2006.

A. K. Mishra, O. Mutlu, and C. R. Das, "A heterogeneous multiple network-on-chip design: an application-aware approach," in Proc. of Design Automation Conference (DAC), pp. 36, May 2013.

A. K. Lusala and J. D. Legat, "A hybrid router combining sdm-based circuit switching with packet switching for on-chip networks," in Proc. of Int. Conf. Reconfigurable Computing and FPGAs (ReConFig), pp. 340-345, Dec. 2010.

H. Matsutani, M. Koibuchi, Y. Yamada, D. F. Hsu, and H. Amano, "Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network," IEEE Trans. Parallel and Distributed Sytems, Vol. 20, no. 8, pp.1126-1141, Aug. 2009. crossref(new window)

Y. Wang, Y. Pan, and X. Yan, and R. Huan, "An On-Line Reconfigurable Four-Ary Tree-Based Network on Chip for Distributed Particle Filters," in Proc. of Int. Conf. Computer Science and Network Technology (ICCSNT), pp. 2102-2106, Dec. 2012.

K. Andreev, H. Racke, "Balanced Graph Partitioning," Theory of Computing Systems, Vol. 39, no. 6, pp. 929-939, Nov. 2006. crossref(new window)

H. Moussa, A. Baghdadi, and M. Jeqequel, "On-chip communication network for flexible multiprocessor turbo decoding," in Proc. of Int. Conf. Information and Communication Technologies: From Theory to Applications (ICTTA), pp. 1-6, April 2008.

D. S. Oh and K. K. Parhi, "Low-complexity switch network for reconfigurable LDPC decoders," IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 18, no. 1, pp. 85-94, Mar. 2009.

P. K. Sahu and S. Chattopadhyay, "A survey on application mapping strategies for Network-on-Chip design," Journal of Systems Architecture, Vol. 59, Issue 1, pp. 66-76, Jan. 2013.

R. P. Dick, D. L. Rhodes, and W. Wolf, "TGFF: Task Graphs for Free," in Proc. of Int. Workshop on Hardware/Software Codesign (CODES/CASHE), pp. 97-101, Mar. 1998.

G. Fen and W. Ning, "A Minumum-Path Mapping Algorithm for 2D Mesh Network on Chip Architecture," in Proc. of Asia Pacific Conf. Circuits and Systems (APCCAS), pp. 1542-1545, Nov. 2008.

Y. Ar, S. Tosun, "TopGen: A New Algorithm for Automatic Topology Generation for Network on Chip Architectures to Reduce Power Consumption," in Proc. of Int. Conf. Application of Information and Communication Technologies (AICT), pp. 1-5, Oct. 2009.