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A Design Of Cross-Shpaed CMOS Hall Plate And Offset, 1/f Noise Cancelation Technique Based Hall Sensor Signal Process System
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 Title & Authors
A Design Of Cross-Shpaed CMOS Hall Plate And Offset, 1/f Noise Cancelation Technique Based Hall Sensor Signal Process System
Hur, Yong-Ki; Jung, Won-Jae; Lee, Ji-Hun; Nam, Kyu-Hyun; Yoo, Dong-Gyun; Yoon, Sang-Gu; Min, Chang-Gi; Park, Jun-Seok;
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 Abstract
This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.
 Keywords
Hall Sensor;Spinning Current Baising;Hall Signal Conditioner;Offset;1/f noise;
 Language
Korean
 Cited by
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