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Robust Placement Method for IR Drop in Power Gating Design
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 Title & Authors
Robust Placement Method for IR Drop in Power Gating Design
Kwon, Seok Il; Han, Tae Hee;
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 Abstract
Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.
 Keywords
IR Drop;
 Language
Korean
 Cited by
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