Advanced SearchSearch Tips
Image Cache for FPGA-based Real-time Image Warping
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Image Cache for FPGA-based Real-time Image Warping
Choi, Yong Joon; Ryoo, Jung Rae;
  PDF(new window)
In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.
real-time image warping;image cache;bilinear interpolation;memory access rate;
 Cited by
FPGA와 Dual Port SRAM 적용한 Radar System Positive Afterimage 고속 정보 표출에 관한 연구,신현종;유형근;

한국위성정보통신학회논문지, 2016. vol.11. 4, pp.1-9
J. Park, S.-C. Byun, and B.-U. Lee, "Lens distortion correction using ideal image coordinates," IEEE Transactions on Consumer Electronics, vol. 55, no. 3, pp. 987-991, Aug. 2009. crossref(new window)

Z. Chen, C. Wu, and H. T. Tsui, "A new image rectification algorithm," Pattern Recognition Letters, vol. 24, no. 1-3, pp. 251-260, Jan. 2003. crossref(new window)

M. Brown and D. G. Lowe, "Automatic panoramic image stitching using invariant features," International Journal of Computer Vision, vol. 74, no. 1, pp. 59-73, Aug. 2007. crossref(new window)

R. Melo, G. Falcao, and J. P. Barreto, "Real-time HD image distortion correction in heterogenous parallel computing systems using efficient memory access patterns," Journal of Real-Time Image Processing, vol. 11, no. 1, pp. 83-91, Jan. 2016. crossref(new window)

J. Park, J. Choi, B.-K. Seo, and J.-I. Park, "Fast stereo image rectification using mobile GPU," in Proc. of the 3rd International Conference on Digital Information Processing and Communications 2013, pp. 485-488, Dubai, UAE, Jan. 2013.

E. Peek, B. Wunsche, and C. Lutterroth, "Using integrated GPUs to perform image warping for HMD," in Proc. of the 29th International Conference on Image and Vision Computing New Zealand, pp. 172-177, Hamilton, New Zealand, Nov. 2014.

W. Wang, J. Yan, N. Xu, Y. Wang, and F.-H. Hsu, "Real-time high-quality stereo vision system in FPGA," IEEE Transactions on Circuits and Systems for Video Technology, vol. 25, no. 10, pp. 1691-1708, Oct. 2015.

H. M. Moon and S. B. Pan, "VLSI architecture of digital image scaler combining linear interpolation and cubic convolution interpolation," Journal of The Institute of Electronics and Information Engineers, vol. 51, no. 3, pp. 579-584, March 2014.

D. Han, J. Choi, and H. C. Shin, "A real-time hardware architecture for image rectification using floating point processing," Journal of The Institute of Electronics and Information Engineers, vol. 51, no. 2, pp. 342-353, Feb. 2014.

J. R. Ryoo, E. S. Lee, and T.-Y. Doh, "An implementation of real-time image warping using FPGA," IEMEK Journal of Embedded Systems and Applications, vol. 9, no. 6, pp. 335-344, 2014. crossref(new window)

P. Greisen, S. Heinzle, M. Gross, and A. P Burg, "An FPGA-based processing pipeline for high-definition stereo video," Journal of Image and Video Processing, vol. 2011, no. 18, pp. 1-13, Nov. 2011.

J.-h Kim, J.-g. Kim, J.-k. Oh, S.-m. Kang, and J.-D. Cho, "Efficient hardware implementation of real-time rectification using adaptively compressed LUT," Journal of Semiconductor Technology and Science, vol. 16, no. 1, pp. 44-57, Feb. 2016. crossref(new window)

J. Moon and J. Kim, "Real-time FPGA rectification implementation combined with stereo camera," in Proc. of the 2015 IEEE International Symposium on Consumer Electronics, pp. 1-2, Madrid, Spain, June 2015.

P. Zicari, "Efficient and high performance FPGA-based rectification architecture for stereo vision," Microprocessors and Microsystems, vol. 37, no. 8, pp. 1144-1154, Nov. 2013. crossref(new window)

X. Yuan, Z. Qinghai, G. Liwei, Z. Mingcheng, and R. K. F. Teng, "Study of a FPGA real-time multi-cameras cylindrical panorama video system with low latency and high performance," in Proc. of the 11th Image, Video and Multidimensional Signal Processing Workshop, pp. 1-4, Seoul, Korea, June 2014.

J. L. Hennessy and D. A. Patterson, Computer Architecture a Quantitative Approach, Morgan Kaufmann Publishers, pp. 375-427, 1996.