A 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching

- Journal title : Journal of the Institute of Electronics and Information Engineers
- Volume 53, Issue 7, 2016, pp.27-38
- Publisher : The Institute of Electronics Engineers of Korea
- DOI : 10.5573/ieie.2016.53.7.027

Title & Authors

A 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching

Shin, Hee-Wook; Jeong, Jong-Min; An, Tai-Ji; Park, Jun-Sang; Lee, Seung-Hoon;

Shin, Hee-Wook; Jeong, Jong-Min; An, Tai-Ji; Park, Jun-Sang; Lee, Seung-Hoon;

Abstract

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of . The proposed composite switching employs the conventional -based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the -based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

Keywords

SAR ADC;

Language

Korean

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