Design of a Inverter-Based 3^{rd} Order ΔΣ Modulator Using 1.5bit Comparators

- Journal title : Journal of the Institute of Electronics and Information Engineers
- Volume 53, Issue 7, 2016, pp.39-46
- Publisher : The Institute of Electronics Engineers of Korea
- DOI : 10.5573/ieie.2016.53.7.039

Title & Authors

Design of a Inverter-Based 3^{rd} Order ΔΣ Modulator Using 1.5bit Comparators

Choi, Jeong Hoon; Seong, Jae Hyeon; Yoon, Kwang Sub;

Choi, Jeong Hoon; Seong, Jae Hyeon; Yoon, Kwang Sub;

Abstract

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is . The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

Keywords

CMOS;1.5 bit comparator;inverter; modulator;

Language

Korean

References

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