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Design of a DI model-based Content Addressable Memory for Asynchronous Cache
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 Title & Authors
Design of a DI model-based Content Addressable Memory for Asynchronous Cache
Battogtokh, Jigjidsuren; Cho, Kyoung-Rok;
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This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.
Cache;CAM;DCVSL;completion signal;
 Cited by
혼합 지연 모델에 기반한 비동기 명령어 캐시 설계,전광배;김석만;이제훈;오명훈;조경록;

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