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Optimization of a Systolic Array BCH encoder with Tree-Type Structure
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 Title & Authors
Optimization of a Systolic Array BCH encoder with Tree-Type Structure
Lim, Duk-Gyu; Shakya, Sharad; Lee, Je-Hoon;
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 Abstract
BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.
 Keywords
BCH code;encoder;parallel processing;tree-type systolic arrays;
 Language
English
 Cited by
 References
1.
X. Zhang and K. K. Parhi, "High-speed Architectures for Parallel long BCH Encoder," in Proc. ACM Great Lakes Symp. VLSI, Apr. 2004, pp.1-6.

2.
T. B. Pei, C Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. on Communications, vol.40, no.4, Apr.1992, pp.653-657. crossref(new window)

3.
K. K. Parhi, "Eliminating the fan-out bottleneck in parallel long BCH encoders," IEEE Trans. on Circuits Syst .1, Reg. Papers, vol.51, no.3, Mar. 2004, pp.512-516. crossref(new window)

4.
Fengbo Liang and Liyang Pan "A CRT-based BCH encoding and FPGA implementation," In Proc, of ICISA, 2010, pp.1-8.

5.
K. Lee, H. G. Kang, J. I. Park, and H. Lee, "A high-speed low-complexity concatenated BCH decoder architecture for 100 Gb/s optical communications," J. of Signal Processing Systems, vol. 66, no. 1, Jan. 2012, pp. 43-55. crossref(new window)

6.
H. Choi, W. Liu, and W. Sung, "VLSI implementation of BCH error correction for multilevel cell NAND flash memory," IEEE Trans. on VLSI Systems, vol.18, no.5, May 2010, pp.843-847. crossref(new window)

7.
S.Lin and D.J. Costello Jr. Error Control Coding, Prentice-Hall, New Jersey, 1983.

8.
Hank Wallace, Error Detection and Correction Using the BCH Code, 2001

9.
Z. Jun. W.Z. gong, H. Q. Sheng, X. Jie, "Optimized design for high-speed parallel BCH encoder," In Proc. of IEEE International Work- shop, 2005, pp.97-100.

10.
A.M. Patel, "A multichannel CRC register," in Proc. of AFIPS Conf., vol.38, 1971, pp.11- 14.

11.
L.V. Cargini, R.D.R. Fangundes, A.E. Bezerra and G.M. Almeida "Parallel algebraic approach of BCH coding in VHDL," in Proc. of ICCGI.2007, p.22.