Constraint Algorithm in Double-Base Number System for High Speed A/D Converters

- Journal title : Journal of Electrical Engineering and Technology
- Volume 3, Issue 3, 2008, pp.430-435
- Publisher : The Korean Institute of Electrical Engineers
- DOI : 10.5370/JEET.2008.3.3.430

Title & Authors

Constraint Algorithm in Double-Base Number System for High Speed A/D Converters

Nguyen, Minh Son; Kim, Man-Ho; Kim, Jong-Soo;

Nguyen, Minh Son; Kim, Man-Ho; Kim, Jong-Soo;

Abstract

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

Keywords

Double-Base number system;Flash ADC;Asymmetric DBIE and constraint algorithm;

Language

English

Cited by

1.

Algorithm and Design of Double-base Log Encoder for Flash A/D Converters,;;;;

한국신호처리시스템학회논문지, 2009. vol.10. 4, pp.289-293

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