JOURNAL BROWSE
Search
Advanced SearchSearch Tips
Constraint Algorithm in Double-Base Number System for High Speed A/D Converters
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Constraint Algorithm in Double-Base Number System for High Speed A/D Converters
Nguyen, Minh Son; Kim, Man-Ho; Kim, Jong-Soo;
  PDF(new window)
 Abstract
In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.
 Keywords
Double-Base number system;Flash ADC;Asymmetric DBIE and constraint algorithm;
 Language
English
 Cited by
1.
Algorithm and Design of Double-base Log Encoder for Flash A/D Converters,;;;;

한국신호처리시스템학회논문지, 2009. vol.10. 4, pp.289-293
 References
1.
V. S. Dimitrov and G. A. Jullien, "A new number representation with applications," IEEE Circuits and Systems Magazine, 2003

2.
J. Yoo, "A TIQ based CMOS flash A/D converter for SoC applications," PhD Thesis, Department of Computer Science and Engineering of the Pennsylvania State University, 2003

3.
http://en.wikipedia.org/wiki/Handshaking_Lemma

4.
V. S. Dimitrov and G. A. Jullien, and W. C. Miller, "Theory and applications of the double-base number system," IEEE Transactions on Computers, vol. 48, pp. 1098-1106, 1999 crossref(new window)

5.
G. Gilbert and J. M. P. Langlois, "Multipath greedy algorithm for canonical representation of numbers in the double base number system," IEEE-NEWCAS Conference, pp. 39-42, 19-22, June 2005

6.
V. Berthe, L. Imbert, and G. A. Jullien, "More on converting numbers to the double-base number system," Research Report LIRMM - 0403 1, Montpellier France, Oct. 2004

7.
Y. Ibrahim, W. C. Miller, Graham A. Jullien, and Vassil S. Dimitrov, "DBNS addition using cellular neural networks," IEEE International Symposium on Circuits and Systems, vol. 4, 2005, pp. 3914-3917

8.
M. Pankaala, A. Paasio, and M. Laiho, "Implementation alternatives of a DBNS adder," 9th International Workshop on Cellular Neural Networks and Their Applications, 2005, pp. 138-141

9.
C. Doche and L. Imbert, "extended double-base number system with applications to elliptic curve cryptography," LNCS 4329, pp. 335-348, Springer-Verlag Berlin/Heidelberg, INDOCRYPT 2006

10.
K. Wangjitman and A. Surarerks, "Addition transducer for double base number system," ISCIT'06, 2006, pp. 994-999

11.
J. Yoo, D. Lee, K. Choi and J. Kim, "A power and resolution adaptive flash analog-to-digital converter," ISLPED'02, 2002, pp. 233-236

12.
D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, "Fat tree encoder design for ultra-high speed flash A/D converters," The 45th Midwest Symposium on Circuits and Systems, vol. 2, pp. 87-90, Aug 2002

13.
D. Lee, J. Yoo, and K. Choi, "Design method and automation of comparator generation for flash A/D converter," IEEE International Symposium on Quality Electronic Design, 2002, pp. 138-142

14.
D. P. Dimitrov and T. K. Vasileva, "8-bit semi-flash A/D converter," Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006, pp. 171-174

15.
J. Kim, M.-H. Kim, and E.-H. Jang, "A new flash A/D converter adopting double base number system," KISPS Journal of Signal Processing and Systems, vol. 9, no. 1, pp. 54-61, 2008