Advanced SearchSearch Tips
Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs
Song, Taigon; Lim, Sung Kyu;
  PDF(new window)
Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it`s physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.
3D IC;Capacitance;Coupling;Face-to-face (F2F);Full-chip;
 Cited by
Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs, IEEE Transactions on Components, Packaging and Manufacturing Technology, 2017, 7, 6, 912  crossref(new windwow)
M. Jung, T. Song, Y. Wan, Y. Peng, and S. K. Lim, "On enhancing power benefits in 3D ICs: block folding and bonding styles perspective," in Proceedings of the 51st Annual Design Automation Conference (DAC), San Francisco, CA, pp. 1-6, 2014.

M. Murugesan, H. Kino, A. Hashiguchi, C. Miyazaki, H. Shimamoto, H. Kobayashi, T. Fukushima, T. Tanaka, and M. Koyanagi, "High density 3D LSI technology using W/Cu hybrid TSVs," in Proceedings of 2011 IEEE International Electron Devices Meeting (IEDM), Washington, DC, pp. 1-4, 2011.

M. Motoyoshi, J. Takanohashi, T. Fukushima, Y. Arai, and M. Koyanagi, "Stacked SOI pixel detector using versatile fine pitch μbump technology," in Proceedings of 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, pp. 1-4, 2011.

C. K. Lee, C. J. Zhan, J. Lau, Y. J. Huang, H. C. Fu, J. H. Huang, Z. C. Hsiao, S. W. Chen, S. Y. Huang, C. W. Fan, et al., "Wafer bumping, assembly, and reliability assessment of μbumps with 5 μm pads on 10 μm pitch for 3D IC integration," in Proceedings of 2012 IEEE 62nd Electronic Components and Technology Conference (ECTC), San Diego, CA, pp. 636-640, 2012.

OpenCores [Online]. Available:

Synopsys, 32/28 nm Generic Library [Online].

D. H. Kim, K. Athikulwongse, and S. K. Lim, "A study of Through-Silicon-Via impact on the 3D stacked IC layout," in Proceedings of the 2009 International Conference on ComputerAided Design, San Jose, CA, pp. 674-680, 2009.

T. Song, A. Nieuwoudt, Y. S. Yu, and S. K. Lim, "Coupling capacitance in face-to-face (F2F) bonded 3D ICs: trends and implications," in Proceedings of 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, pp. 529-536, 2015.