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Device Coupling Effects of Monolithic 3D Inverters
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 Title & Authors
Device Coupling Effects of Monolithic 3D Inverters
Yu, Yun Seop; Lim, Sung Kyu;
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The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness TILD and dielectric constant εr of the inter-layer distance (ILD), the doping concentration Nd (Na), and length Lg of the channel, and the side-wall length LSW where the stacked FETs are coupled are studied. When Nd (Na) < 1016 cm-3 and LSW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when Nd (Na) > 1016 cm-3 or LSW > 20 nm, the shift decreases and increases, respectively. M3INVs with TILD ≥ 50 nm and εr ≤ 3.9 can neglect the interaction between the stacked FETs, but when TILD or εr do not meet the above conditions, the interaction must be taken into consideration.
3D integrated circuit (3D IC);Coupling;Monolithic 3D IC;Parasitic extraction;Threshold voltage;
 Cited by
Interlayer coupling effect on the performance of monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness, Japanese Journal of Applied Physics, 2017, 56, 4S, 04CC02  crossref(new windwow)
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