Converter Utilization Ratio Enhancement in the THD Optimization of Cascaded H-Bridge 7-level Inverters

- Journal title : Journal of Power Electronics
- Volume 16, Issue 1, 2016, pp.173-181
- Publisher : The Korean Institute of Power Electronics
- DOI : 10.6113/JPE.2016.16.1.173

Title & Authors

Converter Utilization Ratio Enhancement in the THD Optimization of Cascaded H-Bridge 7-level Inverters

Khamooshi, Reza; Namadmalan, Alireza; Moghani, Javad Shokrollahi;

Khamooshi, Reza; Namadmalan, Alireza; Moghani, Javad Shokrollahi;

Abstract

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

Keywords

Cascaded H-bridge multi-level inverter;Optimization Methods;Switch Utilization Ratio;Total Harmonic Distortion;

Language

English

References

1.

H. M. Pirouz and M. T. Bina, “Modular multilevel converter based STATCOM topology suitable for medium-voltage unbalanced systems,” Journal of Power Electronics, Vol. 10, No.5, pp. 572-578, Sep. 2010.

2.

L. Haw, M. Dahidah, and H. Almurib, “SHE–PWM Cascaded Multilevel Inverter With Adjustable DC Voltage Levels Control for STATCOM Applications,” IEEE Trans. Power Electron.,Vol. 29, No.12, pp. 6433-6444, Dec. 2014.

3.

N.K. Kumar and K. Sivakumar, “A quad two-level inverter configuration for four-pole induction-motor drive with single DC link,” IEEE Trans. Ind. Electron. Vol. 62, No.1, pp. 105-112, Jan. 2015.

4.

R. Kaarthik, K. Gopakumar, J. Mathew, and T. Undeland,“Medium-voltage drive for induction machine with multilevel dodecagonal voltage space vectors with symmetric triangles,” IEEE Trans. Ind. Electron. Vol. 62, No.1, pp. 79-87, Jan. 2015.

5.

J. Chivite-Zabalza, P. Izurza-Moreno, D. Madariaga, G. Calvo, and M. Rodríguez, “Voltage balancing control in 3-level neutral-point clamped inverters using triangular carrier PWM modulation for FACTS applications,” IEEE Trans. Power Electron., Vol. 28, No.10, pp. 4473-4484, Oct. 2013.

6.

L. Yushan, B. Ge, H. Abu-Rub, and F. Peng, “An effective control method for three-phase quasi-z-source cascaded multilevel inverter based grid-tie photovoltaic power system,” IEEE Trans. Ind. Electron. Vol. 61, No.12, pp. 6794-6802, Dec. 2014.

7.

C. Gu, H. S. Krishnamoorthy, P. N. Enjeti, Z. Zheng, and Y. Li, “A medium-voltage matrix converter topology for wind power conversion with medium frequency transformers,” Journal of Power Electronics, Vol.14, No.6, pp. 1166-1177, Nov. 2014.

8.

M. Malinowski, K. Gopakumar, J. Rodriguez, M. A. Pérez, “A survey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron. Vol. 57, No.7, pp. 2197-2206, Jul. 2010.

9.

C. Buccella, C. Cecati, M. G. Cimoroni, and K. Razi, “Analytical method for pattern generation in five-level cascaded H-bridge inverter using selective harmonic elimination,” IEEE Trans. Ind. Electron. Vol. 61, No. 11, pp. 5811-5819, Nov. 2014.

10.

R. Salehi, N. Farokhnia, M. Abedi, and S. H. Fathi, “Elimination of low order harmonics in multilevel inverters using genetic algorithm,” Journal of Power Electronics, Vol. 11, No. 2, pp. 132-139, Mar. 2011.

11.

B. Jacob and M. R. Baiju, “A new space vector modulation scheme for multilevel inverters which directly vector quantize the reference space vector,” IEEE Trans. Ind. Electron. Vol. 62, No.1, pp. 88-95, Jan. 2015.

12.

W. Jiang, W. Li, Z. Wu, Y. She, and Z. Tao, “Space-vector pulse-width modulation algorithm for multilevel voltage source inverters based on matrix transformation and including operation in the over-modulation region,” IETPower Electron., Vol. 7, No.12, pp. 2925-2933, Dec. 2014.

13.

F. Filho, H. Z. Maia, T. H. A. Mateus, B. Ozpineci, L. M. Tolbert, and J. O. P. Pinto, “Adaptive selective harmonic minimization based on ANNs for cascade multilevel inverters with varying DC sources,” IEEE Trans. Ind. Electron. Vol. 60, No.5, pp.1955-1962, May 2013.

14.

J. Napoles, A. J. Watson, J. J. Padilla, J. I. Leon, L. G. Franquelo, P. W. Wheeler, and M. A. Aguirre, “Selective harmonic mitigation technique for cascaded H-bridge converters with non-equal DC link voltages,” IEEE Trans. Ind. Electron. Vol. 60, No.5, pp. 1963-1971, May 2013.

15.

B. Li, D. Xu, and D. Xu, “Circulating current harmonics suppression for modular multilevel converters based on repetitive control,” Journal of Power Electronics, Vol. 14, No.6, pp. 1100-1108, Nov. 2014.

16.

N. Yousefpoor, S.H. Fathi, N. Farokhniaand, and H. A. Abyaneh, “THD minimization applied directly on the line-to-line voltage of multilevel inverters,” IEEE Trans. Ind. Electron. Vol. 59, No. 1, pp. 373-380, Jan. 2012.

17.

P. Roshankumar, P. P. Rajeevan, K. Mathew, K. Gopakumar, J .I. Leon, and L. G. Franquelo,“A five-level inverter topology with single-DC supply by cascading a flying capacitor inverter and an H-bridge,” IEEE Trans. Power Electron., Vol. 27, No. 8, pp. 3505-3512, Aug. 2012.