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A New Orthogonal Signal Generator with DC Offset Rejection for Single-Phase Phase Locked Loops
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  • Journal title : Journal of Power Electronics
  • Volume 16, Issue 1,  2016, pp.310-318
  • Publisher : The Korean Institute of Power Electronics
  • DOI : 10.6113/JPE.2016.16.1.310
 Title & Authors
A New Orthogonal Signal Generator with DC Offset Rejection for Single-Phase Phase Locked Loops
Huang, Xiaojiang; Dong, Lei; Xiao, Furong; Liao, Xiaozhong;
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 Abstract
This paper presents a new orthogonal signals generator (OSG) with DC Offset rejection for implementing a phase locked loop (PLL) in single-phase grid-connected power systems. An adaptive filter (AF) based on the least mean square (LMS) algorithm is used to constitute the OSG in this study. The DC offset in the measured grid voltage signal can be significantly rejected in the developed OSG technique. This generates two pure orthogonal signals that are free from the DC offset. As a result, the DC offset rejection performance of the presented single-phase phase locked loop (SPLL) can be enhanced. A mathematical model of the developed OSG and the principle of the adaptive filter based SPLL (AF-SPLL) are presented in detail. Finally, simulation and experimental results demonstrate the feasibility of the proposed AF-SPLL.
 Keywords
Adaptive filter;DC offset;Least mean square;Orthogonal signals generator;Phase locked loop;
 Language
English
 Cited by
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