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Dickson Charge Pump with Gate Drive Enhancement and Area Saving
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  • Journal title : Journal of Power Electronics
  • Volume 16, Issue 3,  2016, pp.1209-1217
  • Publisher : The Korean Institute of Power Electronics
  • DOI : 10.6113/JPE.2016.16.3.1209
 Title & Authors
Dickson Charge Pump with Gate Drive Enhancement and Area Saving
Lin, Hesheng; Chan, Wing Chun; Lee, Wai Kwong; Chen, Zhirong; Zhang, Min;
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This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.
Chip size;Dickson charge pump;Efficiency;External capacitor;Fibonacci charge pump;High amplitude;
 Cited by
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