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An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices
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 Title & Authors
An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices
Yoon, Heung Sun; Park, Jong Kang; Kim, Jong Tae;
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As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.
3D-integrated SRAM;soft error;EDC;ECC;EDAC;
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M.-Ch. Tsai, T.-C. Wang, and T. T. Hwang, "Through-Silicon Via Planning 3-D Floorplanning," IEEE Trans. on VLSI, Vol. 19, No. 8, pp.1448-1457, 2011. crossref(new window)

R.C. Baumann, "Soft errors in commercial integrated circuits," Int'l J. of High Speed Electronics and Systems, Vol. 14, No. 2, pp.299-309, 2004.

S.M. Abbas, S. Lee, S. Baeg, S. Park, "An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory," IEEE Trans. on Computers, Vol. 63, No. 8, pp.2094-2098, 2014. crossref(new window)

E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, T. Toba, "Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule," IEEE Trans. on Electron Devices, Vol. 57, No. 7, pp.1527-1538, 2010. crossref(new window)

L.-X. Huang, H.-G. Xie, S.-L. Niu, "Monte Carlo Simulation of Scaling Effect on SEI and MBU Cross Sections by High Energy Protons," Int'l Workshop on Monte Carlo Codes & MCNEG 2007 meeting, 2007.

L.-J. Chang, Y.-J. Huang, and J.-F. Li, "Area and reliability efficient ECC scheme for 3D RAMs," IEEE Int'l Symp. on VLSI-DAT, pp.1-4, 2012.

K. Puttaswamy, and G.H. Loh, "3D-integrated SRAM components for high-performance microprocessors," IEEE Trans. on Computers, Vol. 58, No. 10, pp. 1369-1381, 2009. crossref(new window)

P. Reed, G. Yeung, and B. Black. "Design aspects of a microprocessor data cache using 3D die interconnect technology," IEEE Int'l Conf. on Integrated Circuit Design and Technology, pp. 15-18, 2005.

J. Borkenhagen, and S. Salvatore, "5th Generation 64-bit PowerPC-Compatible Commercial Processor Design," IBM White Paper, 1999.

W. Bryg,and J. Alabado, "The ultrasparc t1 processor-reliability, availability, and serviceability," Whitepapers: UltraSPARC Processors Documentation, 2005.

M.-Y. Hsiao, "A Class of Optimal Minimum Oddweight-column SEC-DED codes," IBM J. of Research and Development, Vol. 14, No. 4, pp.395-401, 1970. crossref(new window)

J. Kim, N. Hardavellas, M. Ken, B. Falsafi, and, J.C. Hoe, "Multi-bit error tolerant caches using two-dimensional error coding," Proc. of 40th IEEE/ACM Int'l Symp. on Microarchitecture, pp.197-209, 2007.

S. Kwon, H.S. Choi, J.K. Park, and J.T. Kim, "Radiation-Induced Soft Error Detection Method for High Speed SRAM Instruction Cache," J-KICS, Vol. 35, No. 6, pp.948-953, 2010.

J.K. Park and J.T. Kim, "An Evolutionary Approach to the Soft Error Mitigation Technique for Cell-Based Design," Advances in Electrical and Computer Eng., Vol. 15, No. 1, pp.33-40, 2015.