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Comparative Analysis on Positive Bias Stress-Induced Instability under High VGS/Low VDS and Low VGS/High VDS in Amorphous InGaZnO Thin-Film Transistors
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 Title & Authors
Comparative Analysis on Positive Bias Stress-Induced Instability under High VGS/Low VDS and Low VGS/High VDS in Amorphous InGaZnO Thin-Film Transistors
Kang, Hara; Jang, Jun Tae; Kim, Jonghwa; Choi, Sung-Jin; Kim, Dong Myong; Kim, Dae Hwan;
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 Abstract
Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high /low and low /high stress conditions through incorporating a forward/reverse sweep and a low/high read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high /low stress is applied. On the other hand, when low /high stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high /low stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low /high stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.
 Keywords
a-IGZO TFT;driving condition of AMOLED;positive bias stress;charge trapping;electron-hole pair generation;
 Language
English
 Cited by
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