Advanced SearchSearch Tips
The Oscillation Frequency of CML-based Multipath Ring Oscillators
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
The Oscillation Frequency of CML-based Multipath Ring Oscillators
Song, Sanquan; Kim, Byungsub; Xiong, Wei;
  PDF(new window)
A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor , which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor an attractive option for lower power applications.
Oscillator;multipath ring oscillator;oscillation frequency;oscillation criterion;oscillation mode;mode gain;forwarding factor;
 Cited by
A Design of 8.5 GHz META-VCO based-on Meta-material using 65 nm CMOS Process, JSTS:Journal of Semiconductor Technology and Science, 2016, 16, 5, 535  crossref(new windwow)
Wooseok Kim, et al., "Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator", Solid-State Circuits, IEEE Journal of, Vol. 49, Num. 3, pp. 657-672, Mar. 2014 crossref(new window)

Talegaonkar, M., et al., "An 8 Gb/s64 Mb/s, 2.34.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS", Solid-State Circuits, IEEE Journal of, Vol. 49, Num. 10, pp. 2228-2242, Oct. 2014 crossref(new window)

Savoj, J., et al., "A Low-Power 0.56.6 Gb/s Wireline Transceiver Embedded inLow-Cost 28 nm FPGAs", Solid-State Circuits, IEEE Journal of, Vol. 48, Num. 11, pp. 2582-2594, Oct. 2013 crossref(new window)

H. Nam, et al., "Cost Effective 60Hz FHD LCD with 800Mbps AiPi Technology," in SID Symposium Digest, 2008.

S. Ozawa, et al., "A 2Gbps/lane Source Synchronous Intra-Panel Interface for Large Size and High Refresh Rate Panel with Automatic Calibration,"in SID Symposium Digest, 2011.

W. Oh, et al., "A 3.4Gbps/lane Low Overhead Clock Embedded Intrapanel Interface for High Resolution and Large-Sized TFT-LCDs," in SID Symposium Digest, 2013.

H. Jeon, et al., "A 3.7Gb/s Clock-embedded Intra- Panel Interface for the Large-sized UHD 120Hz LCD TV Application," in SID Symposium Digest, 2014.

Seog-Jun Lee, et al., "'A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme", Solid-State Circuits, IEEE Journal of, Vol. 32, Num. 2, pp. 289-291, Feb. 1997 crossref(new window)

Akinori Matsumoto, et al., "A Design Method and Developments of a Low-Power and High- Resolution Multiphase Generation System", Solid- State Circuits, IEEE Journal of, Vol. 43, Num. 4, pp. 831-843, Apr. 2008 crossref(new window)

Mohan, S.S.; et al., "Differential ring oscillators with multipath delay stages," Proceedings of the IEEE Custom Integrated Circuits Conference, pp.503,506, 18-21 Sept. 2005.

Straayer, M.Z. and Perrott, M.H., "A Multi-Path Gated Ring Oscillator TDCWith First-Order Noise Shaping", Solid-State Circuits, IEEE Journal of, pp. 1089-1098, Apr. 2009.

Hafez, A.A. and Chih-Kong Ken Yang, "Design and Optimization of Multipath Ring Oscillators", Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 58, Num. 10, pp. 2332-2345, Oct. 2011

Zuow-Zun Chen; Tai-Cheng Lee, "The Design and Analysis of Dual-Delay-Path Ring Oscillators," IEEE Transactions on Circuits and Systems I: Regular Papers , vol.58, no.3, pp.470,478, March 2011

Behzad Razavi, "A study of phase noise in CMOS oscillators", Solid-State Circuits, IEEE Journal of, Vol. 31, Num. 3, pp. 331-343, Mar. 1996 crossref(new window)

Chenming Hu, ''Low-Voltage CMOS Device Scaling," in ISSCC Digestof Technical, pp. 86-87, Feb. 1994