JOURNAL BROWSE
Search
Advanced SearchSearch Tips
Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels
Park, Hwan-Wook; Lim, Hyun-Wook; Kong, Bai-Sun;
  PDF(new window)
 Abstract
This paper presents a half-rate current-integrating DFE receiver with sub-unit interval (sub-UI) inter-symbol interference (ISI) cancellation. By having a single additional DFE tap in each data path, the proposed DFE receiver can minimize BER degradation due to input pattern dependency and feedback tap latency problems in conventional current-integrating DFE receivers. The proposed DFE receiver was designed and fabricated in a 45 nm CMOS process, whose measurement results indicated that the BER bathtub width is increased from 0.235 UI to 0.315 UI (34% improvement) at BER level.
 Keywords
Decision feedback equalization;inter-symbol interference;current integration;multi-drop channel;
 Language
English
 Cited by
1.
6-Gbps Single-ended Receiver with Continuous-time Linear Equalizer and Self-reference Generator, Journal of the Institute of Electronics and Information Engineers, 2016, 53, 9, 54  crossref(new windwow)
 References
1.
Y. Yoon, et al., "A multidrop bus design with resistor-based impedance matching on nonuniform impedance lines," IEEE TCAS-I, vol.58, no.6, pp.1264-1276, June 2011

2.
Seung-Jun Bae, et al., "A 2-Gb/s CMOS integrating two-tap DFE receiver for four-drop single-ended signaling," IEEE TCAS-I, vol.56, no. 8, pp.1645-1656, 2009

3.
T. O. Dickson, et al., "A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology," IEEE JSSC, vol.44, no. 4, pp.1298-1305, 2009

4.
L. Chen, et al., "A scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS," IEEE ISSCC, pp.180-181, Feb. 2009

5.
J. F. Bulzacchelli, et al., "A 28-Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32-nm SOI CMOS technology," IEEE JSSC, vol.PP, no. 99, p.1, Dec. 2012