Publisher : The Institute of Electronics Engineers of Korea
DOI : 10.5573/JSTS.2016.16.1.143
Title & Authors
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier Han, Sangwoo; Lim, Jongtae; Kim, Jongsun;
A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just . The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.
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