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An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
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 Title & Authors
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
Han, Sangwoo; Lim, Jongtae; Kim, Jongsun;
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A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just . The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N
DLL;multiplying DLL;MDLL;frequency multiplier;clock multiplier;multi-phase clock;
 Cited by
A 2–4 GHz fast-locking frequency multiplying delay-locked loop, IEICE Electronics Express, 2017, 14, 2, 20161056  crossref(new windwow)
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