Publisher : The Institute of Electronics Engineers of Korea
DOI : 10.5573/JSTS.2016.16.1.143
Title & Authors
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier Han, Sangwoo; Lim, Jongtae; Kim, Jongsun;
A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just . The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N
M. Demirkan, et al, "A pulse-based ultra-wideband transmitter in 90-nm CMOS for WPANs," IEEE J. Solid-State Circuits, 43, No. 12, pp. 2820-2828, 2008
R. Farjad-Rad, et al, "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips," IEEE J. Solid-State Circuits, 37, no. 12, pp. 1804-1812, 2002.
Q. Du, et al, "A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction," IEEE Trans. Circuits Syst. II, Vol. 53, pp. 1205-1209, 2006.
G. Park, H. Kim, and Jongsun Kim, "A reset-free anti-harmonic anti-harmonic programmable MDLLbased frequency multiplier", J. Semiconductor Technology and Science, Vol. 13, no. 5, pp. 459-464, Oct. 2013.
S. Han, J. Kim, and Jongsun Kim, "Programmable fractional-ratio frequency multiplying clock generator", IET Electronics Letters, Vol. 50, no. 3, pp. 163-165, 2014.