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An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
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 Title & Authors
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
Han, Sangwoo; Lim, Jongtae; Kim, Jongsun;
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 Abstract
A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just . The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N
 Keywords
DLL;multiplying DLL;MDLL;frequency multiplier;clock multiplier;multi-phase clock;
 Language
English
 Cited by
 References
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Q. Du, et al, "A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction," IEEE Trans. Circuits Syst. II, Vol. 53, pp. 1205-1209, 2006. crossref(new window)

4.
G. Park, H. Kim, and Jongsun Kim, "A reset-free anti-harmonic anti-harmonic programmable MDLLbased frequency multiplier", J. Semiconductor Technology and Science, Vol. 13, no. 5, pp. 459-464, Oct. 2013. crossref(new window)

5.
S. Han, J. Kim, and Jongsun Kim, "Programmable fractional-ratio frequency multiplying clock generator", IET Electronics Letters, Vol. 50, no. 3, pp. 163-165, 2014. crossref(new window)