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Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications
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 Title & Authors
Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications
Wang, Wei; Xu, Hongsong; Huang, Zhicheng; Zhang, Lu; Wang, Huan; Jiang, Sitao; Xu, Min; Gao, Jian;
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 Abstract
Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green`s functions (NEGF) solved self - consistently with Poisson`s equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.
 Keywords
CNTFET;NEGF;LDDS;SCE;hetero-material-gate;
 Language
English
 Cited by
 References
1.
Lu, R. F., Lu, Y. P., & Lee, S. Y., "Terahertz response in single-walled carbon nanotube transistor: a real-time quantum dynamics simulation", Nanotechnology, Vol. 20, no. 50, pp. 505401 ,2009. crossref(new window)

2.
Kienle, D., & Leonard, F.,"Terahertz response of carbon nanotube transistors", Phys Rev Lett, Vol. 103, no. 2, pp. 026601, 2009. crossref(new window)

3.
Tans, S. J., Verschueren, A. R. M., & Dekker, C., "Room-temperature transistor based on a single carbon nanotube", Nature, Vol. 393, no. 7, pp. 49-52, 1998. crossref(new window)

4.
Hazeghi, A., Krishnamohan, T., & Wong, H., "Schottky-barrier carbon nanotube field-effect transistor modeling", IEEE Trans Electron Dev, Vol. 54, no. 3, pp. 439-445, 2007. crossref(new window)

5.
Guo, J., Lundstrom, M., & Datta, S. ,"Performance projections for ballistic carbon nanotube fieldeffect transistors", Appl Phys Lett; Vol. 80, no. 17, pp. 3192-3194, 2002. crossref(new window)

6.
Fiori, G., Iannaccone, G., & Klimeck, G.,"A threedimensional simulation study of the performance of carbon nanotube field-effect transistors with doped reservoirs and realistic geometry", IEEE Trans Electron Dev, Vol. 53, no. 8, pp. 1782-1788, 2006. crossref(new window)

7.
Orouji, A. A., & Arefinia, Z, "Detailed simulation study of a dual material gate carbon nanotube fieldeffect transistor", Phys E: Low - dimensional Syst Nanostructures, Vol. 41, no. 10, pp. 552-557, 2009.

8.
Arefinia, Z., & Orouji, A. A., "Quantum simulation study of a new carbon nanotube field-effect transistor with electrically induced source/drain extension", IEEE Trans Device Mater Reliab, Vol. 9, no. 2, pp. 237-243, 2009. crossref(new window)

9.
Xia, T. S., Register, L. F., & Banerjee, S. K., "Simulation study of the carbon nanotube field effect transistors beyond the complex band structure effect", Solid-State Electron, Vol. 49, no. 3, pp. 860-864, 2005. crossref(new window)

10.
Guo, J., Hasan, S., & Javey, A., "Assessment of high-frequency performance potential for carbon nanotube transistors", IEEE Trans Nanotechnol, Vol. 4, no. 6, pp. 715-721, 2005. crossref(new window)

11.
Chen, L., & Pulfrey, D. L., "Comparison of p-i-n and n-i-n carbon nanotube FETs regarding highfrequency performance", Solid - State Electron, Vol. 53, no. 9, pp. 935-939, 2009. crossref(new window)

12.
Liu, X. H., & Zhang J. S., "Theoretical study of transport characteristics of CNTFET with HALOLDD doping structure based on NEGF quantum theory", Acta Phys. Sin, Vol. 61, no. 10, pp. 107302, 2012.

13.
K. Zoheir, M. H. Sheikhi, A. Zarifkar, "Design dependent cut off frequency of nano transistors near the ultimate performance limit", International Journal of Modern Physics B, Vol. 21, on. 32, pp. 1250196-1250110, 2012.

14.
Z. Kordrostami, M. Hossein Sheikhi, Abbas Zarifkar, "Influence of Channel and Underlap Engineering on the High-Frequency and Switching Performance of CNTFETs", IEEE Trans. Nanotechnol, Vol. 11, on. 3, pp. 526-533, 2012. crossref(new window)

15.
Taqi N. Buti, Seiki Ogura, Nivo Rovedo, Kentaroh Tobimatsu, "A New Asymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half- Micrometer n-MOSFET Design for Reliability and Performance", IEEE Trans.Electron Devices, Vol. 38, on. 8, pp. 1757-1764, 1991. crossref(new window)

16.
W. Wang, T. Zhang, L. Zhang, et al, "High -frequency and switching performance investigations of novel lightly doped drain and source hetero - material - gate CNTFET", Materials Science in Semiconductor Processing, Vol. 21, pp. 132-139, 2014. crossref(new window)

17.
Chongwu Z, Jing K, Erhan Y & Hongjie D, "Modulated chemical doping of individual carbon nanotubes", Science, Vol. 290 no. 5496 pp. 1552-1555, 2000. crossref(new window)

18.
Jia C, Christian K, Ali A & Phaedon A, "Selfaligned carbon nanotube transistors with charge transfer doping", Appl. Phys. Lett. 86 123108, 2005. crossref(new window)

19.
Reza, Y., Kamyar, S., & Mohammad, K. M., "Numerical Study of Lightly Doped Drain and Source Carbon Nanotube Field Effect Transistors", IEEE Trans Electron Dev, Vol. 57, no. 4, pp. 765-771, 2010. crossref(new window)

20.
Kordrostami, Z., Hossein, S. M., & Zarifkar, A., "Design dependent cutoff frequency of nanotransistors near the ultimate performance limit", International Journal of Modern Physics B, Vol. 26, no. 32, pp. 1250196, 2012. crossref(new window)

21.
Kumar, J. M., "Two-Dimensional Analytical Modeling of Fully Depleted DMG SOI MOSFET and Evidence for Diminished SCEs", IEEE Trans Electron Dev, Vol. 51, no. 4, pp. 569-574, 2004. crossref(new window)

22.
Long, W., Ou, H. J., Kuo, J. M., & Ken K. C., "Dual-Material Gate (DMG) Field Effect Transistor", IEEE Trans Electron Dev, Vol. 46, no. 5, pp. 865-870, MAY, 1999. crossref(new window)

23.
Chris Dwyer, Moky Cheung, and Daniel J. Sorin, "Semi - empirical spice models for Carbon Nanotube FET logic", IEEE Conference on Nanotechnology, pp. 386-388, 2004.

24.
Burke PJ, "An RF circuit model for carbon nanotubes", IEEE Trans. Nanotechnol., pp. 393-396, 2002.

25.
Yamacli S, Avci M, "Accurate SPICE compatible CNT interconnect and CNTFET models for circuit design and simulation", Mathematical and Computer Modelling, Vol. 58, no. 1, pp. 368-378, 2013. crossref(new window)

26.
Rosenblatt S, Yaish Y, Park J, et al, "High performance electrolyte gated carbon nanotube transistors", Nano. Let., Vol. 2, no. 8, pp. 869-872, 2002. crossref(new window)

27.
Guo J, Goasguen S, Lundstrom M, et al, "Metal -insulator - semiconductor electrostatics of carbon nanotubes", Applied Physics Letters, Vol. 81, no. 8, pp. 1486-1488, 2002 crossref(new window)

28.
Binh-Son L, Thanh-Tri V, Trong-Tu B, "SRAM Cell for High Noise Margin and Soft Errors Tolerance in Nanoscale Technology", Computing, Management and Telecommunications, pp. 96-100, 2014

29.
Sheng L, Yong-Bin k & Fabrizio L, "Design of a Ternary Memory Cell Using CNTFET", IEEE Trans. Nanotechnol., Vol. 11, no. 5, pp. 1019-1024, 2012. crossref(new window)