JOURNAL BROWSE
Search
Advanced SearchSearch Tips
Critical Review of Current Trends in ASIC Writing and Layout Analysis
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Critical Review of Current Trends in ASIC Writing and Layout Analysis
Vikram, Abhishek; Agarwal, Vineeta;
  PDF(new window)
 Abstract
Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.
 Keywords
ASIC (Application Specific Integrated Circuit);VLSI (Very Large Scale Integration);defects;lithography;mask;pattern classification;RET (Resolution Enhancement Technique);
 Language
English
 Cited by
 References
1.
J. H. Bruning, "Optical Lithography ... 40 years and holding", Proc. SPIE Vol. 6520, pp. 652004:1-13, 2007.

2.
D. Alles, et al., "EBES, A practical electron lithographic system", IEEE Trans. Electron Devices, ED-22, 1975.

3.
H. Jeong, et al., "Optical projection system for gigabit random access memories", JVST, Vol. 49, pp. 713, 1995.

4.
Matsuyama, et al., "Lithographic lens: its history and evolution", Proc. SPIE Microlithography, 2006.

5.
Wolfgang Arden, et al, "More-than-Moore" White Paper, International Roadmap Committee, ITRS 2010.

6.
Chris. A. Mack, J. D. Byers, "Exploring the Capabilities of Immersion Lithography Through Simulation", Optical Microlithography XVII, SPIE Vol. 5377, pp. 428-441, 2004.

7.
Vadim Banine and Roel Moors, "Plasma sources for EUV lithography exposure tools", J. Phys. D: Appl. Phys. Vol. 37 3207, 2004.

8.
Harry Shields, et al, "Laser-produced plasma light source for extreme ultraviolet lithography", Proceedings of the IEEE Vol 90 , Issue 10, pp 1689-1695, Oct 2002. crossref(new window)

9.
Hung-Fei Kuo, Wei-Chen Wu, "Forming Freeform Source Shapes by Utilizing Particle Swarm Optimization to Enhance Resolution in Extreme UV Nanolithography", IEEE Transactions on Nanotechnology, Vol. 14, Issue 2, pp 322-329, 2015. crossref(new window)

10.
Mai, J et al, "Low-Cost Nanolithography", IEEE Nanotechnology Magazine, Vol. 5, Issue 3, pp 25-28, 2011.

11.
Igor V. Fomenkov, et al, "Laser Produced Plasma Light Source for EUVL", Proc. SPIE Advanced Lithography 2010.

12.
David C. Brandt, et al, "Laser Produced Plasma EUV Sources for Device Development and HVM", SPIE Advanced Lithography, 2012.

13.
The International Technology Roadmap for Semiconductors, ITRS 2013.

14.
Cheng-Chi Wu, et al, "An instruction-based highthroughput lossless decompression algorithm for ebeam direct-write system", Proc. SPIE 9423, Alternative Lithographic Technologies VII, Vol. 94231P, 2015.

15.
Christoph Hohle, et al, "Verification of E-Beam direct write integration into 28nm BEOL SRAM technology", Proc. SPIE 9423, Alternative Lithographic Technologies VII, Vol. 94231B, 2015.

16.
Isabelle Servin, et al, "Ready for multi-beam exposure at 5kV on MAPPER tool: lithographic and process integration performances of advanced resists/stack", Proc. SPIE 9423, Alternative Lithographic Technologies VII, Vo. 94231C, 2015.

17.
Kalaiselvi, S.M.P., et al, "Neon soft x-ray lithography source based on low energy fast miniature plasma focus device", Plasma Sciences held with 2014 IEEE International Conference on High-Power Particle Beams, 2014 IEEE 41st International Conference on, pp 1-12, 2014.

18.
"The Promise of DSA Technology for Nanoscale Manufacturing", The Institute for Molecular Engineering website, The University of Chicago.

19.
G.S. Khaira, et al, "Evolutionary Optimization of Directed Self-Assembly of Triblock Copolymers on Chemically Patterned Substrates", ACS Macro Letters, Vol. 3, pp. 747-752, 2014. crossref(new window)

20.
Williams Charles S, Becklund Orville A. "Introduction to the optical transfer functions", New York: Wiley, 1989.

21.
Chris A. Mack, "Corner Rounding and Round Contacts", The Lithography Expert, Summer 2000.

22.
Kun Yuan, Jae-seok Yang, Pan, D.Z, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, Issue 2, pp. 185-196, 2010. crossref(new window)

23.
Chin-Hsiung Hsu, Yao-Wen Chang, Nassif S.R, "Simultaneous Layout Migration and Decomposition for Double Patterning Technology, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Issue 2, pp. 284-294, 2011. crossref(new window)

24.
Hailong Yao, Yici Cai, Wei Zhao, "WIPAL: Window-based parallel layout decomposition in double patterning lithography", 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2012.

25.
Xianhua Ke, Wen, L.V., Shiyuan Liu, "Ant colony algorithm for layout decomposition in double/multiple patterning lithography", 2015 China Semiconductor Technology International Conference (CSTIC), pp. 1-3, 2015.

26.
Yasmine Badr, Ko-wei Ma, Puneet Gupta, "Layout pattern-driven design rule evaluation", Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 905307, 2014.

27.
Xiaoqing Xu, Cline, B., Yeric, G., et al., "Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 5, pp. 699-712, 2015. crossref(new window)

28.
Yongchan Ban, Lucas, K., Pan, D., "Flexible 2D layout decomposition framework for spacer-type double pattering lithography", 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 789-794, 2011.

29.
Kodama, C., Ichikawa, H., et al, "Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 5, pp. 753-765, 2015. crossref(new window)

30.
Schellenberg, F.M., Capodieci, L. "Adoption of OPC and the impact on design and layout", IEEE Proceedings Design Automation Conference, pp 89-92, 2001.

31.
John S. Petersen, et al, "High transmission attenuated PSM - Benefits and Limitations through a validation study of 33%, 20% and 6% transmission masks", Optical Microlithography XIII, Vol 4000, 2000.

32.
Tae-Seung Eom, et al, "Comparative Study of Binary Intensity Mask and Attenuated Phase Shift Mask using Hyper-NA Immersion Lithography for Sub-45nm Era", Proc. of SPIE Vol. 6924, 69240H, 2008.

33.
Norihiro Yamamoto et. al., "Mask Topography Effect with Polarization at Hyper-NA" Proc. SPIE 6154, 2006.

34.
Kazuya Sato et. al., "Mask 3D Effect on 45nm Imaging using Attenuated PSM", Proc. SPIE 6520, 2007.

35.
Natalia Davydova, et al, "Black border, mask 3D effects: covering challenges of EUV mask architecture for 22nm node and beyond", Proc. SPIE. 9231, 30th European Mask and Lithography Conference, Vol. 923102, 2014.

36.
Reiji Kanaya, et al, "An improved virtual aberration model to simulate mask 3D and resist effects", Proc. SPIE. 9426, Optical Microlithography XXVIII, Vol. 94261O, 2015.

37.
L. Collins, "Design freedom gets the brush-off [electronics design]", IET Engineering & Technology, Vol.3, Issue 13, pp. 38-41, 2008.

38.
Schellenberg, F M, "Design for Manufacturability in the Semiconductor Industry: the Litho/Design workshops", Proc. International Conference on VLSI Design, IEEE Computer Society Press, pp 111-119, 1999.

39.
Gu, A. and Zakhor, A., "Optical Proximity Correction With Linear Regression" IEEE Transactions on Semiconductor Manufacturing, Vol. 21, Issue 2, pp. 263-271, 2008. crossref(new window)

40.
Melvin III, Lawrence S., et al, "Three Dimensional Mask Effects in OPC Process Model Development From First Principles Simulation", 24th European Mask and Lithography Conference, pp. 1-8, 2008.

41.
Shiyan Hu, et al, "Pattern Sensitive Placement Perturbation for Manufacturability", IEEE Transactions on VLSI Systems, Vol. 18, Issue 6, pp 1002-1006, 2010. crossref(new window)

42.
Hung-Fei Kuo, Wei-Chen Wu, "Forming Freeform Source Shapes by Utilizing Particle Swarm Optimization to Enhance Resolution in Extreme UV Nanolithography", IEEE Transactions on Nanotechnology, Vol. 14, Issue 2, pp. 322-329, 2015. crossref(new window)

43.
Pan, D.Z., et al, "Design for Manufacturing With Emerging Nanolithography", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol. 32, Issue 10, pp. 1453-1472, 2013. crossref(new window)

44.
Jue-Chin Yu, et al, "Library-Based Illumination Synthesis for Critical CMOS Patterning", IEEE Transactions on Image Processing, Vol. 22, Issue 7, pp. 2811-2821, 2013. crossref(new window)

45.
Gupta, P, et al, "Wafer Topography-Aware Optical Proximity Correction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 12, 2006.

46.
Jain, A., Alam, S.M., Pozder, S., Jones, R.E., "Thermal-electrical co-optimization of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints", Computers & Digital Techniques, IET Vol. 5, Issue 3, pp 169-178, May 2011 crossref(new window)

47.
Jhaveri, T., et al, "Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 29, Issue 4, pp 509-527, 2010. crossref(new window)

48.
Yang Xu, et al, "OPERA: optimization with ellipsoidal uncertainty for robust analog IC design", 42nd Design Automation Conference, 2005. Proceedings, pp 632-637, June 2005

49.
Wong A. K, "Some thoughts on the IC designmanufacture interface", IEEE Design & Test of Computers, Vol. 22 , Issue 3, pp 206-213, June 2005. crossref(new window)

50.
Burmen, A., et al, "Robust design and optimization of operating amplifiers", Industrial Technology, 2003 IEEE International Conference on Vol. 2:2, pp. 745-750, Dec 2003.

51.
Fontanelli, A., et al, "Early addressing IC and package relationship allows an overall better quality of complex SOC", Quality Electronic Design, ISQED 2000. Proceedings. IEEE, pp 121-126, 2000.

52.
Nassif, S.R., "Technology modeling and characterization beyond the 45nm node", Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific, pp 219, 2008

53.
Le Denmat, J.C., et al, "Tracking of design related defects hidden in the random defectivity in a production environment", Advanced Semiconductor Manufacturing Conference, 2009. IEEE, SEMI, pp 5-13, 2009.

54.
Mitra, S., et al,"Robust System Design to Overcome CMOS Reliability Challenges", Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, Vol. 1, Issue 1, pp 30-41, 2011. crossref(new window)

55.
Young, C., et al, "Using design based binning to improve defect excursion control for 45nm production", Semiconductor Manufacturing, 2007. ISSM 2007. International Symposium on, pp 1-3, 2007

56.
Miao Wu, et al, "Leakage in CMOS devices induced by pattern-dependent microloading effect", Semiconductor Electronics, 2012 10th IEEE International Conference on,. pp 440-443, 2012.

57.
Jianfeng Luo, et al, "A layout dependent full-chip copper electroplating topography model", Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, pp 133-140, 2005.

58.
Kai-Ti Hsu, et al, "A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.31, Issue 10, pp. 1546-1557, 2012. crossref(new window)

59.
Hong-Yan Su, et al, "A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 1, pp. 95-108, 2015. crossref(new window)

60.
F. Aurenhammer, "Voronoi diagrams - a survey of fundamental geometric data structure", ACM Computing Survey CSUR Vol. 23, Issue 3, pp. 345-405, 1991. crossref(new window)

61.
E. Papadopoulou, "Critical Area Computation for Missing Material Defects in VLSI Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.20, Issue 5, pp. 583-597, 2001. crossref(new window)

62.
Sandeep K. Dey, et al, "Topology and contextbased pattern extraction using line-segment Voronoi diagram",Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX, Vol. 942706, 2015.

63.
E. Papadopoulou, "Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.30, Issue 5, pp. 704-717, 2011. crossref(new window)

64.
R V Joshi, et al,"Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction", IEEE Transactions on Very Large Scale Integration VLSI Systems, Vol.23, Issue 3, pp. 534-543, 2015. crossref(new window)

65.
Pardeep Kumar, et al, "Fast and accurate lithography simulation using cluster analysis in resist model building", J. Micro/Nanolith. MEMS MOEMS, 2015.

66.
Chi-Yuan Hung, et al, "Increasing post OPC layout verification coverage using a full-chip simulation based verification method", Proc. SPIE, Advanced Microlithography Technologies, Vol. 5645, Issue 315, 2005.