A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector

Title & Authors
A 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
Kwon, Dae-Hyun; Rhim, Jinsoo; Choi, Woo-Young;

Abstract
A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $\small{2^{31}-1}$ PRBS input data has 0.011-UI rms jitter.
Keywords
Bang-bang phase detector;clock and data recovery;multiphase;
Language
English
Cited by
References
1.
J.-K. Kim, et al., "A Fully Integraed 0.13-um CMOS 40-Gbs/ Serial Link Transceiver, " Solid-State Circuits, IEEE Journal of, vol. 44, no. 5, pp. 1510-1521, May 2009.

2.
J. Lee, et al., "A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology," Solid-State Circuits, IEEE Journal of, vol. 38, no. 12, pp. 2181-2190, May 2009.

3.
J. W. Jung, et al., "A 25-Gb/s 5mW CMOS CDR/deserializer", Solid-State Circuits, IEEE Journal of, vol. 48, no. 3, pp. 684-697, Mar. 2013.

4.
K.-S. Kwak, et al., "Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits", Circuits and Systems II, IEEE Transactions on, vol. 61, no. 4, pp. 239-243, Apr. 2014.

5.
J. Lee, et al., "Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits", Solid-State Circuits, IEEE Journal of, vol. 39, no. 9, pp. 1571-1580, Sep. 2004.

6.
D.-H. Kwon, et al.,"A Clock and Data Recovery Circuit with Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor", Circuits and Systems I, IEEE Transactions on, vol. 62, no. 6, pp. 1472-1480, Jun. 2015.

7.
J. Lee, et al.,"A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control", Solid-State Circuits, IEEE Journal of, vol. 29, no. 8, pp. 1482-1490, Dec. 1994.

8.
W.-Y. Lee, et al.,"A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation", Circuits and Systmes I, IEEE Transactions on, vol. 59, no. 11, pp. 2581-2528, Nov. 2012.