Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

- Journal title : JSTS:Journal of Semiconductor Technology and Science
- Volume 16, Issue 3, 2016, pp.319-329
- Publisher : The Institute of Electronics Engineers of Korea
- DOI : 10.5573/JSTS.2016.16.3.319

Title & Authors

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

Na, Seung-in; Kim, Susie; Yang, Youngtae; Kim, Suhwan;

Na, Seung-in; Kim, Susie; Yang, Youngtae; Kim, Suhwan;

Abstract

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

Keywords

Excess loop delay;clock jitter;behavioral simulation;DAC linearity;continuous-time delta-sigma modulator;

Language

English

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