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Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators
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 Title & Authors
Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators
Na, Seung-in; Kim, Susie; Yang, Youngtae; Kim, Suhwan;
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 Abstract
High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.
 Keywords
Excess loop delay;clock jitter;behavioral simulation;DAC linearity;continuous-time delta-sigma modulator;
 Language
English
 Cited by
 References
1.
P. Malcovati, et al., "Behavioral modeling of switched-capacitor sigma-delta modulators", IEEE Trans. Circuits Syst. I, vol. 50, no. 3, pp. 352-364, Mar. 2003. crossref(new window)

2.
M. keller, et al., "A method for the discrete-time simulation of continuous-time Sigma-delta modulators", in Proc. IEEE ISCAS, May. 2007.

3.
G. G. E. Gielen, et al., "An analytical integration method for the simulation of continuous-time ${\Delta}{\Sigma}$ Modulators," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3. pp. 389-399, Mar. 2004. crossref(new window)

4.
Category: Control Systems, File: SD Toolbox [Online], Available: http://www.mathworks.com/matlabcentral/fileexchange

5.
M. Ortmanns, Continuous-Time Sigma-Delta AD Conversion, Springer.

6.
R. Schreier, et al.,, "Delta-sigma modulators employing continuous-time circuitry," IEEE Trans. Circuits Syst. I, vol. 43, no. 4, pp. 324-332, Apr. 1996. crossref(new window)

7.
R. Schreier, G. C. Temes, Understanding Delta-Sigma Data Converters.

8.
S. Pavan , "Excess loop delay compensation in continuous-time delta-sigma modulators", IEEE TCAS-II, vol. 55, no. 11, pp. 1119-1123, Nov. 2008.

9.
J. Cherry, et al., "Excess loop delay in continuous-time delta-sigma modulators," IEEE TCAS-II, vol. 46, no. 4, pp. 376-389, Apr. 1999.

10.
C-Y. Ho, et al., "A 4.5mW CT self-coupled ${\Delta}{\Sigma}$ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation," ISSCC Dig. Tech. Papers, pp. 274-276, Feb. 2015.

11.
K. Lee, "Mixed CT/DT cascaded sigma-delta modulator", J. Semicond. Technol. Sci., vol. 9, no. 4, pp. 233-239, Dec. 2009. crossref(new window)

12.
P. Shettigar, et al., "Design techniques for wideband single-bit Continuous-time modulators with FIR feedback DACs", IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2865-2879, Dec. 2012. crossref(new window)

13.
S.-J. Huang, et al., "A 1.2 V 2 MHz BW 0.084 mm2 CT ADC with 97.7 dBc THD and 80 dB DR using low-latency DEM," in IEEE ISSCC Dig. Tech. Papers, pp. 172-173, Feb. 2009.

14.
X. Chen, "A Wideband low-power continuous-time delta-sigma modulator for next generation wireless applications", Ph.D. dissertation, Oregon State Univ.

15.
P. M. Chopp, et al., "Analysis of clock-jitter effects in continuous-time ${\Delta}{\Sigma}$ modulators using discrete-time models", IEEE Trans. Circuits Syst. I, vol. 56, no. 6, pp. 1134-1145, Jun. 2009. crossref(new window)

16.
M. Ortmanns, et al., "Compensation of finte gain-bandwidth induced errors in continuous-time sigma-delta Modulators", IEEE Trans. Circuits Syst. I, vol. 51, no. 6, pp. 1088-1099, Jun. 2004. crossref(new window)

17.
K. Matsukawa, et al., "A 69.8 dB SNDR 3rd-order continuous-time delta-sigma modulator with a ultimate low power tuning system for a worldwide digital TV-receiver," in Proc. IEEE CICC, Sep. 2010.