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All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
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 Title & Authors
All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0
Seong, Kihwan; Lee, Won-Cheol; Kim, Byungsub; Sim, Jae-Yoon; Park, Hong-June;
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 Abstract
A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies , consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.
 Keywords
Multi-phase;ring oscillator;digitally controlled oscillator (DCO);phase-locked loop;
 Language
English
 Cited by
 References
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