JOURNAL BROWSE
Search
Advanced SearchSearch Tips
Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC
Vijayaraj, M.; Balamurugan, K.;
  PDF(new window)
 Abstract
Today`s multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.
 Keywords
SoC;NoC;Docket-NoC;Multiprocessor;Mesh topology;
 Language
English
 Cited by
 References
1.
Bahn J. H. and Bagherzadeh N. "A generic traffic model for on-chip interconnection Networks", International Workshop on Network-on-Chip Architectures, pp. 22-29, 2009.

2.
A. Balakrishnan and A. Naeemi, "Interconnect network analysis of many-core chips," IEEE Trans. on Electron Devices, vol. 58, no. 9, pp. 2831-2837, 2011. . crossref(new window)

3.
W. H. Hu, C. Wang, and N. Bagherzadeh, "Design and analysis of a mesh-based wireless network-on-chip," J. Supercomputing, vol. 71, no. 8, pp. 2330-2846, 2014.

4.
Chand Mal Samota, Naveen Choudhary and Dharm Singh' Performance Evaluation of Turn Model based Routing using LBDR', Int. J. Computer Applications, vol.7, No. 2, pp.15-18, 2014.

5.
A. Ben Ahmed and A. Ben Abdallah, "Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures," J Parallel and Distributed Computing, vol. 74, no. 4, pp. 2229-2240, 2014. crossref(new window)

6.
J. Wu, "A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model," IEEE Tran. Computers, vol. 52, no. 9, pp. 1154-1169, 2003. crossref(new window)

7.
Eghbal A, Yaghini P. M, Pedram H. and Zarandi H. R.,"Designing fault-tolerant network-on-chip router architecture", Int. J. Electronics, Vol.97, No.10, pp.1181-1192, 2010. crossref(new window)

8.
Flich J, Rodrigo S. and Duato J., "An efficient implementation of distributed routing algorithms for NoCs", Second ACM/IEEE International Symposium on Networks-on-Chip, pp. 87-96, 2008.

9.
Z. Wang, H. Ligang, W. Jinhui, G. Shuqin, and W. Wuchen, "Comparison research between XY and odd-even routing algorithm of a 2-dimension 3x3 mesh topology network-on-chip," in Proceedings of WRI Global Congress on Intelligent Systems, vol. 3, pp. 329-333, 2009.

10.
Gupta N, Kumar M, Laxmi V. and Gaur M.S.' ${\sigma}LBDR$: Congestion-aware logic based distributed routing for 2D NoC', 19th International Symposium on VLSI Design and Test (VDAT), pp.1-6, 2015.

11.
John M.R, James R, Jose J. and Isaac E,. 'A Novel Energy Efficient Source Routing for Mesh NoCs', Fourth International Conference on Advances in Computing and Communications (ICACC), pp.125-129, 2014.

12.
T. Moscibroda and O. Mutlu, "A case for bufferless routing in on-chip networks," ACM SIGARCH Computer Architecture News, vol. 37, no. 3, p. 196, 2009. crossref(new window)

13.
T. T. Ye, L. Benini, and G. De Micheli, "Packetization and routing analysis of on-chip multiprocessor networks", J. Syst. Architecture, vol. 50, no. 2-3, pp. 81-104, 2004. crossref(new window)

14.
Lotfi-Kamran P, Rahmani A, Daneshtalab M, Afzali-Kusha A. and Navabi Z., "Edxy a low cost congestion-aware routing algorithm for network-on-chips",J. Syst. Architecture, Vol. 56, No.7, pp.256-264, 2010. crossref(new window)

15.
Nickray M, Dehyadgari M. and Afzali-Kusha, A., "Adaptive routing using context-aware agents for networks on chips", Fourth International Design and Test Workshop (IDT), pp.1-6, 2010.

16.
A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark, and J. Duato, "Region-based routing: A mechanism to support efficient routing algorithms in NoCs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 3, pp. 356-369, 2009. crossref(new window)

17.
Prasun Ghosal and Tuhin Subhra Das, "Improved Extended XY On-chip Routing In Diametrical 2D Mesh NOC",Int.J. VLSI design & Communication Systems, vol.3, no.5, pp.199-200, 2012.

18.
C. Killian, C. Tanougast, F. Monteiro, and A. Dandache, "Online routing fault detection for reconfigurable NoC," in Proceedings - 2010 International Conference on Field Programmable Logic and Applications, pp. 183-186, 2010.

19.
Sancho J.C, Robles A. and Duato, J., "On the relative behavior of source and distributed routing in NOWs using Up/Down routing schemes", Ninth Euromicro Workshop on Parallel and Distributed Processing, pp.11-18, 2011.