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Design of a G-Share Branch Predictor for EISC Processor
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 Title & Authors
Design of a G-Share Branch Predictor for EISC Processor
Kim, InSik; Jun, JaeYung; Na, Yeoul; Kim, Seon Wook;
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This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.
Microarchitecture;Branch predictor;Digital logic circuits;
 Cited by
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