JOURNAL BROWSE
Search
Advanced SearchSearch Tips
Design of a G-Share Branch Predictor for EISC Processor
facebook(new window)  Pirnt(new window) E-mail(new window) Excel Download
 Title & Authors
Design of a G-Share Branch Predictor for EISC Processor
Kim, InSik; Jun, JaeYung; Na, Yeoul; Kim, Seon Wook;
  PDF(new window)
 Abstract
This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.
 Keywords
Microarchitecture;Branch predictor;Digital logic circuits;
 Language
English
 Cited by
 References
1.
Sprangle, E. and Carmean, D., "Increasing processor performance by implementing deeper pipelines," Proc. 29th Annual Int. Symp. on Computer Architecture, 2002.

2.
Advanced Digital Chips Inc., "Extenable Instruction Set Computer,"

3.
Shien-Tai Pan, Kimming So, and Joseph T. Rahmeh, "Improving the accuracy of dynamic branch prediction using branch correlation," In Proc. of the fifth int. conf. on Architectural support for programming languages and operating systems, 1992.

4.
Xilinx, "Virtex-5 Family Overview,"

5.
Tse-Yu Yeh and Yale N. Patt, "Two-level adaptive training branch prediction," In Proc. of the 24th annual int. symp. on Microarchitecture, 1991.

6.
Reinhold P. Weicker, "Dhrystone: a synthetic systems programming benchmark," Magazine Communications of the ACM, vol. 27, issue 10, pp. 1013-1030, October 1984. crossref(new window)