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High Performance CMOS Charge Pumps for Phase-locked Loop
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 Title & Authors
High Performance CMOS Charge Pumps for Phase-locked Loop
Rahman, Labonnah Farzana; Ariffin, NurHazliza Bt; Reaz, Mamun Bin Ibne; Marufuzzaman, Mohammad;
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 Abstract
Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.
 Keywords
CMOS;Charge pump (CP);Phase-locked-loop (PLL);Current mismatch;
 Language
English
 Cited by
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