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Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications
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 Title & Authors
Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications
Baek, Ki-Ju; Kim, Yeong-Seuk; Na, Kee-Yeol;
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This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (RON) and 50% drain conductance (gds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.
High-voltage laterally double-diffused metal-oxide-semiconductor (HVLDMOS);MOSFET;Dual gate oxide (DGOX);Mixed-signal application;
 Cited by
J. Mitros, C. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster, D. Mosher, and T. R. Efland, IEEE Trans. Electron Dev., 48, 1751 (2001). [DOI:] crossref(new window)

R. A. Bianchi, F. Monsieur, F. Blanchet, C. Raynaud, and O. Noblanc, IEDM Tech. Dig., 137 (2008).

H. Chang, J. J. Jang, M. H. Kim, E. K. Lee, D. E. Jang, J. S. Park, J. H. Jung, C. J. Yoon, D. R. Bae, and C. H. Park, International symposium on power semiconductor devices & IC’s, 217 (2012).

P. Hower, S. Pendharkar, and J. Smith, IEE Proc. Circuits Devices Syst., 153, 73 (2006). [DOI:] crossref(new window)

F. Udrea, IET Circuits Devices Syst., 1, 357 (2007). [DOI:] crossref(new window)

R. Sithanandam and M. J. Kumar, Semicond. Sci. Technol., 25, 1 (2010). [DOI:]

J. B. Ha, H. S. Kang, K. J. Baek, and J. H. Lee, IEEE Electron Dev. Lett., 31, 8 (2010). [DOI:] crossref(new window)

K. Y. Na, K. J. Baek, G. W. Lee, and Y. S. Kim, IEEE Trans. Electron Dev., 60, 3515 (2013). [DOI:] crossref(new window)

K. J. Baek, D. H. Lee, Y. S. Kim, and K. Y. Na, Electron Lett., 49, 1486 (2013). [DOI:] crossref(new window)

M. Y. Hong, IEEE Trans. Electron Dev., 40, 2222 (1993). [DOI:] crossref(new window)

M. Shrivastava, M. S. Baghini, H. Gossner, and V. R. Rao, IEEE Trans. Electron Dev., 57, 448 (2010). [DOI:] crossref(new window)

C. Bulucea, S. R. Bahl, W. D. French, J. J. Yang, P. Francis, T. Harjono, V. Krishnamurthy, J. Tao, and C. Parker, IEEE Trans. Electron Dev., 57, 2363 (2010). [DOI:] crossref(new window)

M. Shur, Appl. Phys. Lett., 54, 162 (1989). [DOI:] crossref(new window)

K. Y. Na, K. J. Baek, and Y. S. Kim, J. Korean Phys. Soc., 52, 1128 (2008). [DOI:] crossref(new window)

MEDICI - Synopsys, User manual, ver. A-2008.09, Synopsys, 2008.

M. Saxena, S. Haldar, M. Gupta, and R. S. Gupta, Solid-State Electronics, 47, 2131 (2003). [DOI:] crossref(new window)

B. J. Baliga, Power semiconductor devices (PWS, Boston, 1996)

J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. Ko, and C. Hu, IEDM Tech Dig., 569 (1992).

W. Long, H. Ou, J. M. Kuo, and K. K. Chin, IEEE Trans. on Electron Dev., 46, 865 (1999). [DOI:] crossref(new window)

R. J. Baker, CMOS - Circuit design, layout, and simulation. 2nd ed. (Wiley, NJ, 2005)