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A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion
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 Title & Authors
A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion
Lee, Youn-Jin; Shidi, Qu; Kim, Young-Chul;
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In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.
Crosstalk;Low Power;Switching activity;On-chip;Bus Encoding;
 Cited by
N. Hanchate, N. Ranganathan, "A line- ar time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise," VLSI Design, 5th International Conference on Embedded Systems and Design., 19th International Conference on, Jan, 2006.

T. Zhang, S. S. Sapatnekar, "Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst, 15(6), pp.624-636, Jan, 2007. crossref(new window)

Harmander Singh, Richard Brown, "Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise," IEEE Trans. On Very Large Scale Integration (VLSI) System, 18(1), pp.166-170, Jan, 2010. crossref(new window)

J. Piestrak Stanislaw, Olivier Sentieys, "Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication," IEEE Trans. On Circuits and System-II, Express Briefs, 57(10), pp. 777-781, Oct, 2010. crossref(new window)

Z. Khan, T. Arslan, A. T. Erdogan, "Low power system on chip bus encoding scheme with crosstalk noise reduction capability," Computer and Digital Techniques, IEEE Proceedings, 153(2), pp.101-108, Mar, 2006. crossref(new window)

S. K. Verma, B. K. Kaushik, "Crosstalk and Power Reduction Using Bus Encoding in RC Coupled VLSI Interconnects," IEEE Third International Conference on Emerging Trends in Engineering and Technology, pp. 735-740, Nov, 2010.

W. W. Hsieh, P.-Y. Chen, C. Y. Wang and T. T. Hwang, "A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design," IEEE Trans. Comput- Aided Des. Integr. Circuits Syst., pp. 2222-2227, Dec, 2007.

P. P. Sotiriadis, A. Chandrakasan, "Low power bus coding techniques considering inter-wire capacitance," Proc. IEEE Custom Integrated Circuits Conf., CICC 2000, pp. 507-510, 2000.

M. R. Stan, W. P. Burleson, "Bus-Invert Coding for Low Power I/O," IEEE Trans on VLSI System, 3(1), pp.49-58, Mar, 1995. crossref(new window)

Chunjie Duan, Anup Tirumala, S. P. Khatri, "Analysis and avoidance of crosstalk in on-chip buses," Hot Interconnects, pp. 133-138, Sep, 2001.

Yan Ahang, J. Lach, K. Skadon, M. R. Stan, "Odd/Even bus invert with two-phase transfer for buses with coupling," Proc. IEEE Low Power Electronics and Design ISLPED, pp.80-83, 2002.

K. Siomalas, "Standardizing Delay Calculation in Verilog," Verilog HDL Conference, Proceedings., 1995 IEEE International, pp. 49-55, Mar, 1955.