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Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints
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 Title & Authors
Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints
Jeong, Seung-Ho; Ahn, Hee-June;
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Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.
video decoder;DVFS;optimal theory;majorization;embedded system;
 Cited by
영상 프레임 디코딩 복잡도 예측을 통한 DVFS 전력감소 방식,안희준;정승호;

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