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A High Speed LDPC Decoder Structure Based on the HSS
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 Title & Authors
A High Speed LDPC Decoder Structure Based on the HSS
Lee, In-Ki; Kim, Min-Hyuk; Oh, Deock-Gil; Jung, Ji-Won;
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 Abstract
This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mcv message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'c and the sign of the previous incoming messages Moldv'c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.
 Keywords
DVB-S2;HSS;LDPC;High Speed;Memory conflict;Memory Structure;
 Language
Korean
 Cited by
1.
유럽형 지상파/케이블/위성 멀티모드 HD 방송 수신이 가능한 통합 수신기 구현,이연성;권기원;김동구;

한국통신학회논문지, 2015. vol.40. 11, pp.2113-2120 crossref(new window)
 References
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M. Gomes, G. Falcao, V. Silva, V. Ferreira, A. Sengo, and M. Falcao. "Flexible parallel architecture for DVB-S2 LDPC decoders. In Global", Telecommunications Conference, 2007. GLOBECOM '07. IEEE, pages 3265 -3269, Washington, USA, November 2007.