Error Corrected K`th order Goldschmidt`s Floating Point Number Division

- Journal title : Journal of the Korea Institute of Information and Communication Engineering
- Volume 19, Issue 10, 2015, pp.2341-2349
- Publisher : The Korean Institute of Information and Commucation Engineering
- DOI : 10.6109/jkiice.2015.19.10.2341

Title & Authors

Error Corrected K`th order Goldschmidt`s Floating Point Number Division

Cho, Gyeong-Yeon;

Cho, Gyeong-Yeon;

Abstract

The commonly used Goldschmidt`s floating-point divider algorithm performs two multiplications in one iteration. In this paper, a tentative error corrected K`th Goldschmidt`s floating-point number divider algorithm which performs K times multiplications in one iteration is proposed. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation in single precision and double precision divider is derived from many reciprocal tables with varying sizes. In addition, an error correction algorithm, which consists of one multiplication and a decision, to get exact result in divider is proposed. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a divider unit. Also, it can be used to construct optimized approximate reciprocal tables.

Keywords

Floating point divider;K`th order Goldschmidt;Error correction Variable latency;

Language

Korean

Cited by

References

1.

V. Lappalainen, et al, "Overview of Research Efforts on Media ISA Extension and their Usage in Video Coding," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 12, pp. 660-670, Aug. 2002.

2.

Taek-Jun Kwon, Jeff Sondeen and Jeff Draper, "Floating-Point and Square Root Implementation using a Taylor-Series Expansion Algorithm," Circuits and Systems Signal Processing Systems, IEEE 50th Midwest Symposium on, pp. 702-705, 2008.

3.

S. F. Oberman and M. J. Flynn, "Design Issues in Division and Other Floating Point Operations," IEEE Transactions on Computer, Vol. C-46, pp. 154-161, Feb. 1997.

4.

D. L. Harris, S. F. Oberman, and M. A. Horowitz, "SRT Division Architectures and Implementations," Proc. 13th IEEE Symp. Computer Arithmetic, Jul. 1997.

5.

Nicolas Louvet, Jean-Michel Muller, and Adrien Panhaleuax, "Newton-Raphson Algorithms for Floating- Point Divsion Using and FMA," ASAP, 2010 21st IEEE International Conference on, pp. 200-207, 2010.

6.

J. A. Pineiro, et al, "High-speed double-precision computation of reciprocal, division, square root and inverse square root ," IEEE transaction on Computers, Vol. 51, No. 12, pp. 1377-1388, Dec. 2002.

7.

M. D. Ercegovac, et al, "Improving Goldschmidt Division, Square Root, and Square Root Reciprocal," IEEE Transactions on Computer, Vol. 49, No. 7, pp.759-763, Jul. 2000.

8.

Sung-Ki Kim, Hong-Bok Song and Gyeong-Yeon Cho, “A Variable Latency Goldschmidt's Floating Point Number Divider,” Journal of the Korea Institute of Maritime Information and Communication Sciences, Vol. 9, No. 2, pp. 380-389, April, 2005.

9.

Gyeong-Yeon Cho, “A Variable Latency K'th Order Newton-Raphson's Floating Point Number Divider,” Journal of IEMEK, Vol. 9, No. 4, pp. 285-292, Oct. 2014.

10.

S. F. Anderson, et al, "The IBM System/360 model 91 Floating Point Execution Unit," IBM Journal of Research and Development, 11(1), pp. 34-53, Jan. 1967.

11.

Timo Viitanen, Pekka Jaakelainen, and Jarmo Takala, "Inexpensive Correctly Rounded Floating-Point Division and Square Root with Input Scaling," Proceedings of the 2013 IEEE Workshop on Signal Processing Systems, SiPS 2013, Oct. 2013.

12.

Bogdan Pasca, "Correctly Rounded Floating-Point Division for DSP-Enabled FPGAs," Field Programmable Logic and Applications 22nd International Conference on, pp. 240-254, Aug. 2012.

13.

P. Markstein, "Computation of elementary functions on the IBM RISC system/6000 processor," IBM Journal of Research and Development, 34(1), pp. 111-119, Jan. 1990

14.

Etic M. Schwarz, "Rounding for Quadratically Converging Algorithm for Division and Square Root," In Proc. 29th Asilomar Conference on Signals and Computers, IEEE, pp. 600-603, 1996

15.

Nicolas Brisebarre, Jean-Michel Muller, and Saurabh Kumar, "Accelerating Correctly Rounded Floating-Point Division when the Divider Is Known in Advance," IEEE Transactions on Computers, Vol. 53, No. 8, pp. 1069-1072, Aug. 2004.

16.

IEEE, IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Standard, Std. 754-1985.