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A 1.88-mW/Gb/s 5-Gb/s Transmitter with Digital Impedance Calibration and Equalizer
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 Title & Authors
A 1.88-mW/Gb/s 5-Gb/s Transmitter with Digital Impedance Calibration and Equalizer
Kim, Ho-Seong; Beak, Seung-Wuk; Jang, Young-Chan;
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This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.
Transmitter;Impedance;Calibration;Equalizer;Signal integrity;
 Cited by
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