Publisher : The Korean Institute of Information and Commucation Engineering
DOI : 10.6109/jkiice.2016.20.1.123
Title & Authors
Hardware Design of High Performance Arithmetic Unit with Processing of Complex Data for Multimedia Processor Choi, Byeong-yoon;
In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.
Ruby B. Lee, "Subword Parallelism with MAX-2," IEEE Micro, vol.16, no. 4, pp.51-59, August 1996.
Ruby B. Lee, "Accelerating Multimedia with Enhanced Microprocessors," IEEE Micro, vol.15, no.2, pp.22-32, April, 1995.
QualComm, Hexagon V2 Programmer's Reference Manual, 80-NB419-1 Rev.A, August 2011.
Israel Koren, Computer Arithmetic Algorithms, ch.5-6, CRC Press, 1993.
Aamir Alam Farooqui, "VLSI Arithmetic for Media Signal Processing," Ph.D dissertation, ECE department, UC. Davis, 2000.
Hyuk-Jun Lee and Michael Flynn, "Designing a Partitionable Multiplier," Stanford University, Technical Report CSL-TR-98-772, October 1998.
Hesham Al-Twaijry and Michael Flynn. "Performance/Area Tradeoffs in Booth Multipliers," Stanford University, Technical Report CSL-TR-95-684, November 1995.
Alexander F. Tenca, Song Park, and Lo'al A. Tawalbeh, "Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution," IEEE Transactions on Computers, vol. 55, no.5, pp.630-635, May 2006.
Stuart F. Oberman, and Ming Y. Siu, "A High-Performance Area-Efficient Multifunction Interpolator," Proc. of the 17th IEEE Symposium on Computer Arithmetic(ARITH'05), pp.271-279, 2005.
M. Roorda, "Method to reduce the sign bit extension in a multiplier that uses the modified booth algorithm," Electronics Letters, vol.22. no.20, pp.1061-1062, 25th September 1986.
Christoper Fritz and Adly T. Farm, "The Interlaced Partition Multiplier," IEEE Trans. on Computer[online], no. 1, pp. 1, PrePrints, doi:10.1109/TC.2015.2481379, Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7274668.