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Design of an NMOS-Diode eFuse OTP Memory IP for CMOS Image Sensors
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 Title & Authors
Design of an NMOS-Diode eFuse OTP Memory IP for CMOS Image Sensors
Lee, Seung-Hoon; Ha, Pan-Bong; Kim, Young-Hee;
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 Abstract
In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.
 Keywords
NMOS-Diode;eFuse;OTP;CMOS image sensor;sensing failure;
 Language
Korean
 Cited by
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