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Design of a Logic eFuse OTP Memory IP
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 Title & Authors
Design of a Logic eFuse OTP Memory IP
Ren, Yongxu; Ha, Pan-bong; Kim, Young-Hee;
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In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is ().
Logic eFuse;OTP;external program volta;small area;
 Cited by
Comparison of Embedded Non-Volatile Memory Technologies and Their Applications[Internet]. Available:


APPLICATION[Internet]. Available:

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