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Design of a Logic eFuse OTP Memory IP
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 Title & Authors
Design of a Logic eFuse OTP Memory IP
Ren, Yongxu; Ha, Pan-bong; Kim, Young-Hee;
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 Abstract
In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (
 Keywords
Logic eFuse;OTP;external program volta;small area;
 Language
Korean
 Cited by
 References
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