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The Design of Transform and Quantization Hardware for High-Performance HEVC Encoder
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 Title & Authors
The Design of Transform and Quantization Hardware for High-Performance HEVC Encoder
Park, Seungyong; Jo, Heungseon; Ryoo, Kwangki;
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 Abstract
In this paper, we propose a hardware architecture of transform and quantization for high-perfornamce HEVC(High Efficiency VIdeo Coding) encoder. HEVC transform decides the transform mode by comparing RDCost to search for the best mode of them. But, RDCost is computed using the bit-rate and distortion which is computed by transform, quantization, de-quantization, and inverse transform. Due to the many calculations and encoding time, it is hard to process high resolution and high definition image in real-time. This paper proposes the method of transform mode decision by comparing sum of coefficient after transform only. We use BD-PSNR and BD-Bitrate which is performance indicator. Based on the experimental result, We confirmed that the decision of transform mode can process images with no significant change in the image quality. We reduced hardware area by assigning different values at the same output according to the transform mode and overlapping coefficient multiplied as much as possible. Also, we raise performance by implementing sequential pipeline operation. In view of the larger process that we used compared with the process of reference paper, Our design has reduced by half the hardware area and has increased performance 2.3 times.
 Keywords
HEVC;Transform;Quantization;Encoder;Transform mode;
 Language
Korean
 Cited by
 References
1.
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2.
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6.
Fraunhofer Heinrich Hertz Institute. HEVC(High Efficiency Video Coding) Reference Model 10.0[Internet]. Available: https://hevc.hhi.fraunhofer.de/svn/svn_HEVCSoftware/tags/HM-10.0/.

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P. K. Meher, S. Y. Park, B. K. Mohanty, K. S. Lim, C. Yeo, "Efficient Integer DCT Architecture for HEVC," IEEE Transaction on circuit and systems for video technology, vol. 24, no. 1, pp. 168-178, Jan. 2014. crossref(new window)