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Hardware Design of In-loop Filter for High Performance HEVC Encoder
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 Title & Authors
Hardware Design of In-loop Filter for High Performance HEVC Encoder
Park, Seungyong; Im, Junseong; Ryoo, Kwangki;
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 Abstract
This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.
 Keywords
HEVC Encoder;In-loop Filter;Deblocking Filter;SAO(Sample Adaptive Offset);Hardware Design;
 Language
Korean
 Cited by
 References
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