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An Efficient Hardware Implementation of Lightweight Block Cipher Algorithm CLEFIA for IoT Security Applications
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 Title & Authors
An Efficient Hardware Implementation of Lightweight Block Cipher Algorithm CLEFIA for IoT Security Applications
Bae, Gi-chur; Shin, Kyung-wook;
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This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.
CLEFIA;lightweight block cipher;information security;IoT security;secret key cryptography;
 Cited by
다중 블록 암호 알고리듬을 지원하는 암호 프로세서,조욱래;김기쁨;배기철;신경욱;

한국정보통신학회논문지, 2016. vol.20. 11, pp.2093-2099 crossref(new window)
ECB/CBC/OFB/CTR 운영모드와 80/128-비트 키 길이를 지원하는 PRESENT 암호 프로세서 설계,김기쁨;조욱래;신경욱;

한국정보통신학회논문지, 2016. vol.20. 6, pp.1163-1170 crossref(new window)
IoT 응용을 위한 초경량 블록 암호 알고리듬 PRESENT의 하드웨어 설계,조욱래;김기쁨;신경욱;

한국정보통신학회논문지, 2016. vol.20. 7, pp.1296-1302 crossref(new window)
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