Publisher : The Korean Institute of Information and Commucation Engineering
DOI : 10.6109/jkiice.2016.20.3.577
Title & Authors
Design of a Time-to-Digital Converter Using Counter Choi, Jin-Ho;
The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from to . But the error range of digital output is from 0 to in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.
Duo Sheng, Ching-Che Chung, Chih-Chung Huang and Jia-Wei Jian, "A High-Resolution and One-Cycle Conversion Time-to-Digital Converter Architecture for PET Omage Applications," in Proceedings of 35th Annual International Conference of the IEEE EMBS, Osaka, Japan, pp.2461-2464, July 2013.
T. Olsson and P. Nilsson, "A Digitally Controlled PLL for Soc Applications," IEEE Journal of Solid State Circuits, vol. 39, no. 5, pp.751-760, May 2004.
Takahiro Fusayasu, "A Fast Integrating ADC Using Precide Time-to-Digital Conversion," IEEE Nuclear Science Symposium Conference Record, pp. 302-304, 2007.
Stephan Henzler, Time-to-Digital Converters, Springer Netherlands, 2010.
S. Rana and K. Pal, "Current Conveyor Simulation Circuits Using Operational Amplifiers," Journal of Physical Sciences, vol. 11, pp.124-132, Aug. 2007.
Matthew Z. Straayer and Michael H. Perrott, "A Multi-Path Gated Ring Oscillator TDC with First-Order noise Shaping," IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, April 2009.