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Education equipment for FPGA-based multimedia player design
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 Title & Authors
Education equipment for FPGA-based multimedia player design
Yu, Yun Seop;
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 Abstract
Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.
 Keywords
Application Specific Integrated Circuits (ASIC);Education Equipment;Engineering Design;Field Programmable Gate Array(FPGA);Multi-Media Player;
 Language
Korean
 Cited by
 References
1.
S. Brown and J. Rose, "FPGA and CPLD architectures: A tutorial," IEEE Design & Test of Computers, vol. 13, no. 2, pp. 42-57, 1996.

2.
E. Monmasson and M. N. Cirstea, "FPGA design methodology for industrial control systems-A review," IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp. 1824-1842, 2007.

3.
M. Tomasi, M. Vanegas, F. Barranco, J. Diaz, and E. Ros, "Real-time architecture for a robust multi-scale stereo engine on FPGA," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 12, pp. 2208-2219, 2012.

4.
A. Kinsman and N. Nicolici, "A VLSI architecture and the FPGA prototype for MPEG-2 audio/video decoding," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, pp. 499-503, 2011.

5.
A. Gupta, V. K. Sehrawat, and M. Khosla, "FPGA based real time human hand gesture recognition system," Procedia Technology vol. 6, pp. 98-107, 2012.

6.
S. A. Christe, M. Vignesh, and A. Kandaswamy "An efficient FPGA implementation of MRI image filtering and tumour characterization using Xilinx system generator," International Journal of VLSI Design & Communication Systems (VLSICS), vol. 2, no. 4, pp. 95-109, 2011.

7.
L. R. Rabiner, "A tutorial on hidden Markov models and selected applications in speech recognition," Proceedings of the IEEE, vol. 77, no. 2, pp. 257-286, 1989.

8.
P. Anandan and R. S. Sabeenian, "Image compression techniques using curvelet, contourlet, ridgelet and wavelet transforms-A review," Biometrics and Bioinformatics, vol. 5, no. 7, pp. 267-270, 2013.

9.
Y. Shishikui, K. Iguchi, S. Sakaida, K. Kazui, and A. Nakagawa, "High-performance video codec for super hivision," Proceedings of the IEEE, vol. 101, no. 1, pp. 130-139, 2013.

10.
Terasic. Altera DE2-115 development and education board [Internet]. Available: http://www.terasic.com.

11.
Terasic. 4.3" LCD touch panel package [Internet]. Available: http://www.terasic.com.

12.
SHARP. NT-335C [Internet]. Available: http://backup.ntrex.co.kr/mart7/upload/pdf/NT-335C.pdf.

13.
Texas Instrument. $PurePath^{(TM)}$ wireless 2.4 GHz RF SoC for wireless digital audio streaming CC8531 [Internet]. Available: http://www.ti.com.

14.
Texas Instrument. Second generation system-on-chip solution for 2.4 GHz IEEE 802.15.4/RF4CE/ZigBee CC2530 [Internet]. Available: http://www.ti.com.

15.
National Instrument. LabView [Internet]. Available: http://www.ni.com/labview.

16.
Altera. Introduction to the Quartus(R) II software, version 13.1, altera corp. San Jose, CA [Internet]. Available: http://www.altera.com.

17.
Altera. Nios II software developer's handbook, altera corp. San Jose, CA [Internet]. Available: http://www.altera.com.