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Design of Lightweight Parallel BCH Decoder for Sensor Network
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 Title & Authors
Design of Lightweight Parallel BCH Decoder for Sensor Network
Choi, Won-Jung; Lee, Je-Hoon;
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This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.
BCH code;Parallel BCH decoder;Syndrome generator;Chien search;
 Cited by
MLC 낸드 플래시 메모리 오류정정을 위한 고속 병렬 BCH 복호기 설계,최원정;이제훈;성원기;

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