Design of Lightweight Parallel BCH Decoder for Sensor Network Choi, Won-Jung; Lee, Je-Hoon;
This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.
S. Lin and D. J. Costello, Error Control Coding, Upper Saddle River, NJ: Prentice Hall, 2004.
R. Martin, et al., "Fault detection and diagnosis for multilevel cell flash memories," Proc. of IMT 2006, pp.1896- 1901, Apr. 2006
S. C. Jang, et. Al., "Design of a parallel BCH decoder for MLC memory," Proc. ISOCC '08, Vol. 3, pp. 46-47, Nov. 2008.
Chen, Yanni and Parhi, K.K. "Small Area Parallel Chien Search Architectures for Long BCH Codes," IEEE Trans. Inform. Theory, Vol. 12, No. 5, pp. 545-549, May. 2004.
Y. J. Lee and H. Y. Yoo and I. C. Park, "Small-area parallel syndrome calculation for strong BCH decoding," Proc. of ICASSP 2012, pp. 1609-1612, March. 2012.
Massey, J, L., "Shift-register synthesis and BCH decoding," IEEE Trans. Inform. Theory, Vol. 15, No. 1, pp. 122-127, Jan. 1969.
J. H. Jeng and T. Y. Truong, "On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm," IEEE Trans. Commun., Vol. 47, No. 10, pp. 1488-1494, Oct. 1999.
R. T. Chien, "Cyclic decoding procedure for the Bose- Chaudguri-Hocquenhem Code," IEEE Trans. Inform. Theory, Vol. 10, No. 10, pp.357-363, Oct. 1964.
S. V. Fedorenko and P. V. Trifonov, "Finding roots of polynomials over finite fields," IEEE Trans. Commun., Vol. 50, No. 11, Nov. 2002.